Discussion:
[PATCH 0/4] Gemini forward-port to kernel v4.14
(too old to reply)
Linus Walleij
2018-04-04 20:34:02 UTC
Permalink
This patch set forward-ports Gemini to v4.14 with as good
support as I can get.

I don't know if all or any patches actually make it through
to the devel list. They are also posted here:

https://dflund.se/~triad/krad/gemini/openwrt/

It would be nice if we could apply this and get a working
modernized base for the Gemini platforms.

The v4.14 is a bit patchy. With v4.16 we will be looking
pretty neat.

Linus Walleij (4):
firmware-utils: Add the DNS-313 image header tool
gemini: Forward-port to v4.14
gemini: Add kernel v4.14 patches
gemini: Delete kernel 4.4 patches

target/linux/gemini/Makefile | 15 +-
.../linux/gemini/base-files/etc/board.d/03_hdparm | 14 +
.../base-files/lib/preinit/05_set_ether_mac_gemini | 25 +-
target/linux/gemini/config-4.14 | 587 ++++
target/linux/gemini/config-4.4 | 165 -
.../files/arch/arm/mach-gemini/include/mach/gmac.h | 21 -
.../linux/gemini/files/arch/arm/mach-gemini/pci.c | 318 --
.../linux/gemini/files/drivers/ata/pata_gemini.c | 234 --
.../files/drivers/net/ethernet/gemini/Kconfig | 31 -
.../files/drivers/net/ethernet/gemini/Makefile | 5 -
.../files/drivers/net/ethernet/gemini/sl351x.c | 2340 -------------
.../files/drivers/net/ethernet/gemini/sl351x_hw.h | 1436 --------
.../gemini/files/drivers/usb/host/ehci-fotg2.c | 258 --
.../gemini/files/drivers/watchdog/gemini_wdt.c | 378 --
target/linux/gemini/image/Makefile | 166 +-
target/linux/gemini/image/dns313-header/Makefile | 34 +
.../gemini/image/dns313-header/dns313-header.c | 239 ++
target/linux/gemini/image/slask.mk | 56 +
.../0001-cache-patch-from-OpenWRT.patch} | 9 +
...0002-pinctrl-gemini-Add-missing-functions.patch | 33 +
...ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch | 51 +
...rl-Add-skew-delay-pin-config-and-bindings.patch | 73 +
...0005-pinctrl-gemini-Use-generic-DT-parser.patch | 112 +
...-gemini-Implement-clock-skew-delay-config.patch | 280 ++
.../0007-pinctrl-gemini-Fix-GMAC-groups.patch | 186 +
...nctrl-gemini-Fix-missing-pad-descriptions.patch | 27 +
...inctrl-gemini-Add-two-missing-GPIO-groups.patch | 25 +
...0-pinctrl-gemini-Fix-usage-of-3512-groups.patch | 25 +
...trl-gemini-Support-drive-strength-setting.patch | 198 ++
...d-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch | 113 +
...s-Add-basic-devicetree-for-D-Link-DNS-313.patch | 272 ++
...RM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch | 27 +
...0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch | 74 +
...-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch | 113 +
...tchdog-gemini-ftwdt010-rename-DT-bindings.patch | 88 +
...gemini-ftwdt010-rename-driver-and-symbols.patch | 527 +++
...watchdog-ftwdt010-Make-interrupt-optional.patch | 93 +
.../0020-soc-Add-SoC-driver-for-Gemini.patch | 113 +
...t-Add-DT-bindings-for-the-Gemini-ethernet.patch | 119 +
...t-Add-a-driver-for-Gemini-gigabit-etherne.patch | 3661 ++++++++++++++++++++
...23-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch | 74 +
.../0024-net-gemini-Depend-on-HAS_IOMEM.patch | 30 +
...-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch | 36 +
...r-gemini-poweroff-Avoid-spurious-poweroff.patch | 80 +
...sb-host-add-DT-bindings-for-faraday-fotg2.patch | 65 +
...28-usb-host-fotg2-add-device-tree-probing.patch | 61 +
...usb-host-fotg2-add-silicon-clock-handling.patch | 99 +
...b-host-fotg2-add-Gemini-specific-handling.patch | 131 +
...RM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch | 178 +
.../linux/gemini/patches-4.4/050-gpio-to-irq.patch | 21 -
.../110-watchdog-add-gemini_wdt-driver.patch | 29 -
.../111-arm-gemini-add-watchdog-device.patch | 33 -
.../112-arm-gemini-register-watchdog-devices.patch | 40 -
.../120-net-add-gemini-gmac-driver.patch | 20 -
.../121-arm-gemini-add-gmac-device.patch | 85 -
.../122-arm-gemini-register-ethernet.patch | 227 --
.../130-usb-ehci-add-fot2g-driver.patch | 133 -
.../131-arm-gemini-add-usb-device.patch | 77 -
.../patches-4.4/132-arm-gemini-register-usb.patch | 65 -
.../140-arm-gemini-add-pci-support.patch | 66 -
.../linux/gemini/patches-4.4/150-gemini-pata.patch | 192 -
target/linux/gemini/raidsonic/config-default | 5 -
target/linux/gemini/raidsonic/target.mk | 17 -
target/linux/gemini/wiligear/target.mk | 10 -
tools/firmware-utils/Makefile | 1 +
tools/firmware-utils/src/dns313-header.c | 239 ++
66 files changed, 8277 insertions(+), 6278 deletions(-)
create mode 100755 target/linux/gemini/base-files/etc/board.d/03_hdparm
create mode 100644 target/linux/gemini/config-4.14
delete mode 100644 target/linux/gemini/config-4.4
delete mode 100644 target/linux/gemini/files/arch/arm/mach-gemini/include/mach/gmac.h
delete mode 100644 target/linux/gemini/files/arch/arm/mach-gemini/pci.c
delete mode 100644 target/linux/gemini/files/drivers/ata/pata_gemini.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/Kconfig
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/Makefile
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x_hw.h
delete mode 100644 target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c
delete mode 100644 target/linux/gemini/files/drivers/watchdog/gemini_wdt.c
create mode 100644 target/linux/gemini/image/dns313-header/Makefile
create mode 100644 target/linux/gemini/image/dns313-header/dns313-header.c
create mode 100644 target/linux/gemini/image/slask.mk
rename target/linux/gemini/{patches-4.4/060-cache-fa.patch => patches-4.14/0001-cache-patch-from-OpenWRT.patch} (79%)
create mode 100644 target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch
create mode 100644 target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch
create mode 100644 target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch
create mode 100644 target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch
create mode 100644 target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch
create mode 100644 target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch
create mode 100644 target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch
create mode 100644 target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch
create mode 100644 target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch
create mode 100644 target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch
create mode 100644 target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch
create mode 100644 target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch
create mode 100644 target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch
create mode 100644 target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch
create mode 100644 target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch
create mode 100644 target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch
create mode 100644 target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch
create mode 100644 target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch
create mode 100644 target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch
create mode 100644 target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch
create mode 100644 target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch
create mode 100644 target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch
create mode 100644 target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch
create mode 100644 target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch
create mode 100644 target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch
create mode 100644 target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch
create mode 100644 target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch
delete mode 100644 target/linux/gemini/patches-4.4/050-gpio-to-irq.patch
delete mode 100644 target/linux/gemini/patches-4.4/110-watchdog-add-gemini_wdt-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/111-arm-gemini-add-watchdog-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/112-arm-gemini-register-watchdog-devices.patch
delete mode 100644 target/linux/gemini/patches-4.4/120-net-add-gemini-gmac-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/121-arm-gemini-add-gmac-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/122-arm-gemini-register-ethernet.patch
delete mode 100644 target/linux/gemini/patches-4.4/130-usb-ehci-add-fot2g-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/131-arm-gemini-add-usb-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/132-arm-gemini-register-usb.patch
delete mode 100644 target/linux/gemini/patches-4.4/140-arm-gemini-add-pci-support.patch
delete mode 100644 target/linux/gemini/patches-4.4/150-gemini-pata.patch
delete mode 100644 target/linux/gemini/raidsonic/config-default
delete mode 100644 target/linux/gemini/raidsonic/target.mk
delete mode 100644 target/linux/gemini/wiligear/target.mk
create mode 100644 tools/firmware-utils/src/dns313-header.c
--
2.14.3
Linus Walleij
2018-04-04 20:34:03 UTC
Permalink
This tool is used to create headers on images for the
D-Link DNS-313.

Signed-off-by: Linus Walleij <***@linaro.org>
---
tools/firmware-utils/Makefile | 1 +
tools/firmware-utils/src/dns313-header.c | 239 +++++++++++++++++++++++++++++++
2 files changed, 240 insertions(+)
create mode 100644 tools/firmware-utils/src/dns313-header.c

diff --git a/tools/firmware-utils/Makefile b/tools/firmware-utils/Makefile
index ba4df640cefa..63c5daca6160 100644
--- a/tools/firmware-utils/Makefile
+++ b/tools/firmware-utils/Makefile
@@ -82,6 +82,7 @@ define Host/Compile
$(call cc,zyimage, -Wall)
$(call cc,mkdhpimg buffalo-lib, -Wall)
$(call cc,mkdlinkfw mkdlinkfw-lib, -lz -Wall --std=gnu99)
+ $(call cc,dns313-header, -Wall)
endef

define Host/Install
diff --git a/tools/firmware-utils/src/dns313-header.c b/tools/firmware-utils/src/dns313-header.c
new file mode 100644
index 000000000000..e69e57e7baaa
--- /dev/null
+++ b/tools/firmware-utils/src/dns313-header.c
@@ -0,0 +1,239 @@
+/*
+ * dns313-header.c
+ *
+ * Program to add the modified U-Boot header to a binary used with
+ * the D-Link DNS-313 boot loader when booting directly from an
+ * EXT2 formatted hard drive.
+ *
+ * The DNS313 use the same header on zImage, ramdisk, rootfs.
+ *
+ * Written by Linus Walleij <***@linaro.org>
+ * License terms: GPLv2
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+/*
+ * This is the U-Boot magic number, so the U-Boot header was used
+ * (obviously) as a template for this custom header.
+ */
+#define IH_MAGIC 0x27051956
+#define HEADER_SIZE 0x68
+
+#define OFFSET_MAGIC 0x00
+#define OFFSET_HCRC 0x04
+#define OFFSET_TIME 0x08
+#define OFFSET_SIZE 0x0c
+#define OFFSET_LOAD 0x10
+#define OFFSET_EP 0x14
+#define OFFSET_DCRC 0x18
+#define OFFSET_OS 0x1c
+#define OFFSET_ARCH 0x1d
+#define OFFSET_TYPE 0x1e
+#define OFFSET_COMP 0x1f
+#define OFFSET_NAME 0x20
+#define NAME_LEN 0x20
+#define OFFSET_MODEL 0x40
+#define MODEL_LEN 0x10
+#define OFFSET_VERSION 0x50
+#define VERSION_LEN 0x10
+#define OFFSET_MAC 0x60
+#define MAC_LEN 6
+
+static const uint32_t crc32_table[256] = {
+ 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL,
+ 0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL,
+ 0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL,
+ 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL,
+ 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL,
+ 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL,
+ 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL,
+ 0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL,
+ 0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL,
+ 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL,
+ 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL,
+ 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL,
+ 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL,
+ 0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL,
+ 0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL,
+ 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL,
+ 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL,
+ 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL,
+ 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL,
+ 0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL,
+ 0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL,
+ 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL,
+ 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL,
+ 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL,
+ 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL,
+ 0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL,
+ 0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL,
+ 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL,
+ 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL,
+ 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL,
+ 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL,
+ 0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL,
+ 0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL,
+ 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL,
+ 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL,
+ 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL,
+ 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL,
+ 0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL,
+ 0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL,
+ 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL,
+ 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL,
+ 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL,
+ 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL,
+ 0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL,
+ 0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL,
+ 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL,
+ 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL,
+ 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL,
+ 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL,
+ 0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL,
+ 0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL,
+ 0x2d02ef8dUL
+};
+
+static uint32_t crc32(uint32_t crc,
+ const unsigned char *buf,
+ unsigned int len)
+{
+ crc = crc ^ 0xffffffffUL;
+ do {
+ crc = crc32_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+ } while (--len);
+ return crc ^ 0xffffffffUL;
+}
+
+static void be_wr(unsigned char *buf, uint32_t val)
+{
+ buf[0] = (val >> 24) & 0xFFU;
+ buf[1] = (val >> 16) & 0xFFU;
+ buf[2] = (val >> 8) & 0xFFU;
+ buf[3] = val & 0xFFU;
+}
+
+int main(int argc, char **argv)
+{
+ int fdin;
+ int fdout;
+ struct stat sb;
+ uint32_t filesize;
+ uint32_t padding;
+ int ret = 0;
+ const char *pathin;
+ const char *pathout;
+ unsigned char *buffer;
+ unsigned char *infop;
+ uint32_t sum;
+ size_t bufsize;
+ size_t bytes;
+ int i;
+
+ if (argc < 3) {
+ printf("Too few arguments.\n");
+ printf("%s <infile> <outfile>\n", argv[0]);
+ }
+
+ pathin = argv[1];
+ pathout = argv[2];
+
+ ret = stat(pathin, &sb);
+ if (ret < 0)
+ return ret;
+
+ filesize = sb.st_size;
+ padding = filesize % 4;
+ printf("INFILE: %s, size: %08x bytes\n", pathin, filesize);
+ /* File + extended header size */
+ bufsize = filesize + HEADER_SIZE;
+
+ printf("Allocate %08x bytes\n", bufsize);
+ buffer = malloc(bufsize);
+ if (!buffer) {
+ printf("OOM: could not allocate buffer\n");
+ return 0;
+ }
+
+ memset(buffer, 0x00, bufsize);
+
+ /* Read file to buffer */
+ fdin = open(pathin, O_RDONLY);
+ if (!fdin) {
+ printf("ERROR: could not open input file\n");
+ return 0;
+ }
+ bytes = read(fdin, buffer + HEADER_SIZE, filesize);
+ if (bytes < filesize) {
+ printf("ERROR: could not read entire file\n");
+ return 0;
+ }
+ close(fdin);
+
+ /* PREP HEADER AND FOOTER */
+ infop = buffer;
+
+ be_wr(buffer + OFFSET_MAGIC, IH_MAGIC);
+
+ /* FIXME: use actual time */
+ be_wr(buffer + OFFSET_TIME, 0x4c06738c);
+ be_wr(buffer + OFFSET_SIZE, filesize);
+
+ /* Load address & entry point */
+ be_wr(buffer + OFFSET_LOAD, 0x00008000);
+ be_wr(buffer + OFFSET_EP, 0x00008000);
+
+ buffer[OFFSET_OS] = 0x05; /* Linux */
+ buffer[OFFSET_ARCH] = 0x02; /* ARM */
+ buffer[OFFSET_TYPE] = 0x02; /* OS kernel image */
+ buffer[OFFSET_COMP] = 0x01; /* gzip */
+
+ /* The vendor firmware just hardcodes this */
+ strncpy(buffer + OFFSET_NAME, "kernel.img", NAME_LEN);
+ buffer[OFFSET_NAME + NAME_LEN - 1] = '\0';
+ strncpy(buffer + OFFSET_MODEL, "dns-313v3", MODEL_LEN);
+ buffer[OFFSET_MODEL + MODEL_LEN - 1] = '\0';
+ strncpy(buffer + OFFSET_VERSION, "2.01b04", VERSION_LEN);
+ buffer[OFFSET_VERSION + VERSION_LEN - 1] = '\0';
+ /* Just some MAC address from the example */
+ buffer[OFFSET_MAC] = 0x00;
+ buffer[OFFSET_MAC + 1] = 0x80;
+ buffer[OFFSET_MAC + 2] = 0xc8;
+ buffer[OFFSET_MAC + 3] = 0x16;
+ buffer[OFFSET_MAC + 4] = 0x81;
+ buffer[OFFSET_MAC + 5] = 0x68;
+
+ /* Checksum payload */
+ sum = crc32(0, buffer + HEADER_SIZE, filesize);
+ be_wr(buffer + OFFSET_DCRC, sum);
+ printf("data checksum: 0x%08x\n", sum);
+
+ /* Checksum header, then write that into the header checksum */
+ sum = crc32(0, buffer, HEADER_SIZE);
+ be_wr(buffer + OFFSET_HCRC, sum);
+ printf("header checksum: 0x%08x\n", sum);
+
+ printf("OUTFILE: %s, size: %08x bytes\n", pathout, bufsize);
+ fdout = open(pathout, O_RDWR|O_CREAT|O_TRUNC,S_IRWXU|S_IRGRP);
+ if (!fdout) {
+ printf("ERROR: could not open output file\n");
+ return 0;
+ }
+ bytes = write(fdout, buffer, bufsize);
+ if (bytes < bufsize) {
+ printf("ERROR: could not write complete output file\n");
+ return 0;
+ }
+ close(fdout);
+
+ free(buffer);
+
+ return 0;
+}
--
2.14.3
Linus Walleij
2018-04-04 20:34:04 UTC
Permalink
This forward-ports the Gemini OpenWRT by taking all the device
tree patches from v4.16-rc2 and backporting on top of v4.14.

The TVE200 graphics are excluded but these were never used by
OpenWRT before. We will fix that when we get there.

On top of this are some WIP patches for USB support.

The Raidsonic image generation was hacked up without any chance
of testing on an actual device.

Signed-off-by: Linus Walleij <***@linaro.org>
---
ChangeLog v3->v4:
- Make sure to use tabs rather than spaces in base-files.
- Use the dns313 image tool from the firmware-utils.
- Break out the addition of the v4.14 patches and the removal
of the v4.4 patches to separate (big) patches.
ChangeLog v2->v3:
- Update the kernel config as indicated by Hauke Martens:
- Regenerate again after rebasing using kernel_oldconfig
dropping a few optimization settings that are now generic
- Drop CFG80211 stuff (module)
- Drop CIFS stuff (module)
- Drop MAC80211 (module)
- Drop wireless drivers (module)
- Enabled OverlayFS
- Added proper DNS-313 boot image generation with the special
file header tool.
- Disable CMA in the kernel
- Enable LZMA compression of the kernel
- Consequently name the nas4220b images nas4220b
- Update preinit MAC detection script to handle also DNS-313
- Add board.d/03_hdparm to set the disk to spin down after
1 minute by default, if we have the hdparm tool installed
ChangeLog v1->v2:
- Processed config through kernel_oldconfig
- Processed patches through make target/linux/{clean,refresh} V=99
---
target/linux/gemini/Makefile | 15 +-
.../linux/gemini/base-files/etc/board.d/03_hdparm | 14 +
.../base-files/lib/preinit/05_set_ether_mac_gemini | 25 +-
.../files/arch/arm/mach-gemini/include/mach/gmac.h | 21 -
.../linux/gemini/files/arch/arm/mach-gemini/pci.c | 318 ---
.../linux/gemini/files/drivers/ata/pata_gemini.c | 234 --
.../files/drivers/net/ethernet/gemini/Kconfig | 31 -
.../files/drivers/net/ethernet/gemini/Makefile | 5 -
.../files/drivers/net/ethernet/gemini/sl351x.c | 2340 --------------------
.../files/drivers/net/ethernet/gemini/sl351x_hw.h | 1436 ------------
.../gemini/files/drivers/usb/host/ehci-fotg2.c | 258 ---
.../gemini/files/drivers/watchdog/gemini_wdt.c | 378 ----
target/linux/gemini/image/Makefile | 166 +-
target/linux/gemini/image/dns313-header/Makefile | 34 +
.../gemini/image/dns313-header/dns313-header.c | 239 ++
target/linux/gemini/image/slask.mk | 56 +
target/linux/gemini/raidsonic/config-default | 5 -
target/linux/gemini/raidsonic/target.mk | 17 -
target/linux/gemini/wiligear/target.mk | 10 -
19 files changed, 477 insertions(+), 5125 deletions(-)
create mode 100755 target/linux/gemini/base-files/etc/board.d/03_hdparm
delete mode 100644 target/linux/gemini/files/arch/arm/mach-gemini/include/mach/gmac.h
delete mode 100644 target/linux/gemini/files/arch/arm/mach-gemini/pci.c
delete mode 100644 target/linux/gemini/files/drivers/ata/pata_gemini.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/Kconfig
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/Makefile
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x_hw.h
delete mode 100644 target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c
delete mode 100644 target/linux/gemini/files/drivers/watchdog/gemini_wdt.c
create mode 100644 target/linux/gemini/image/dns313-header/Makefile
create mode 100644 target/linux/gemini/image/dns313-header/dns313-header.c
create mode 100644 target/linux/gemini/image/slask.mk
delete mode 100644 target/linux/gemini/raidsonic/config-default
delete mode 100644 target/linux/gemini/raidsonic/target.mk
delete mode 100644 target/linux/gemini/wiligear/target.mk

diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile
index f02e4b179f7f..276489c7496c 100644
--- a/target/linux/gemini/Makefile
+++ b/target/linux/gemini/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2009-2013 OpenWrt.org
+# Copyright (C) 2009-2018 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
@@ -9,15 +9,18 @@ include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=gemini
BOARDNAME:=Cortina Systems CS351x
-SUBTARGETS:=raidsonic wiligear
-FEATURES:=squashfs pci rtc
-CPU_TYPE:=fa526
+FEATURES:=squashfs pci rtc usb dt gpio
MAINTAINER:=Roman Yeryomin <***@advem.lv>
+CPU_TYPE:=fa526

-KERNEL_PATCHVER:=4.4
+KERNEL_PATCHVER:=4.14

-KERNELNAME:=zImage
+define Target/Description
+ Build firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU
+endef

include $(INCLUDE_DIR)/target.mk

+KERNELNAME:=zImage dtbs
+
$(eval $(call BuildTarget))
diff --git a/target/linux/gemini/base-files/etc/board.d/03_hdparm b/target/linux/gemini/base-files/etc/board.d/03_hdparm
new file mode 100755
index 000000000000..b6b886394247
--- /dev/null
+++ b/target/linux/gemini/base-files/etc/board.d/03_hdparm
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+# Enables spin-down of the hard drive when not in
+# use, if the hdparm utility from Busybox is installed.
+
+which hdparm > /dev/null
+if [ ! $? -eq 0 ] ; then
+ exit 0
+fi
+
+# Spin down after 1 minute if inactive
+if [ -b /dev/sda ] ; then
+ hdparm -S 12 /dev/sda > /dev/null
+fi
diff --git a/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini b/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini
index 499608120e4c..1ce5c8067ef0 100644
--- a/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini
+++ b/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini
@@ -1,13 +1,28 @@
#!/bin/sh

set_ether_mac() {
+ # Most devices have a standard "VCTL" partition
CONFIG_PARTITION="$(grep "VCTL" /proc/mtd | cut -d: -f1)"
- MAC1="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f2|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"
- MAC2="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f8|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"
+ if [ ! -z $CONFIG_PARTITION ] ; then
+ MAC1="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f2|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"
+ MAC2="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f8|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')"

- ifconfig eth0 hw ether $MAC1 2>/dev/null
- ifconfig eth1 hw ether $MAC2 2>/dev/null
+ ifconfig eth0 hw ether $MAC1 2>/dev/null
+ ifconfig eth1 hw ether $MAC2 2>/dev/null
+ return 0
+ fi
+
+ # The DNS-313 has a special field in its RedBoot
+ # binary that we need to check
+ CONFIG_PARTITION="$(grep "RedBoot" /proc/mtd | cut -d: -f1)"
+ if [ ! -z $CONFIG_PARTITION ] ; then
+ DEVID="$(dd if=/dev/mtdblock0 bs=1 skip=119508 count=7 2>/dev/null)"
+ if [ "x$DEVID" = "xdns-313" ] ; then
+ MAC1="$(dd if=/dev/mtdblock0 bs=1 skip=119540 count=6 2>/dev/null | hexdump -n6 -e '/1 ":%02X"' | sed s/^://g)"
+ ifconfig eth0 hw ether $MAC1 2>/dev/null
+ return 0
+ fi
+ fi
}

boot_hook_add preinit_main set_ether_mac
-
diff --git a/target/linux/gemini/files/arch/arm/mach-gemini/include/mach/gmac.h b/target/linux/gemini/files/arch/arm/mach-gemini/include/mach/gmac.h
deleted file mode 100644
index 04ca5699fa49..000000000000
--- a/target/linux/gemini/files/arch/arm/mach-gemini/include/mach/gmac.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Gemini GMAC specific defines
- *
- * Copyright (C) 2008, Paulius Zaleckas <***@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __NET_GEMINI_PLATFORM_H__
-#define __NET_GEMINI_PLATFORM_H__
-
-#include <linux/phy.h>
-
-struct gemini_gmac_platform_data {
- char *bus_id[2]; /* NULL means that this port is not used */
- phy_interface_t interface[2];
-};
-
-#endif /* __NET_GEMINI_PLATFORM_H__ */
diff --git a/target/linux/gemini/files/arch/arm/mach-gemini/pci.c b/target/linux/gemini/files/arch/arm/mach-gemini/pci.c
deleted file mode 100644
index 51cd44754c7d..000000000000
--- a/target/linux/gemini/files/arch/arm/mach-gemini/pci.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Support for Gemini PCI Controller
- *
- * Copyright (C) 2009 Janos Laube <***@gmail.com>
- * Copyright (C) 2009 Paulius Zaleckas <***@teltonika.lt>
- *
- * based on SL2312 PCI controller code
- * Storlink (C) 2003
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/pci.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#define GEMINI_PCI_IOSIZE_1M 0x0000
-
-#define GEMINI_PCI_PMC 0x40
-#define GEMINI_PCI_PMCSR 0x44
-#define GEMINI_PCI_CTRL1 0x48
-#define GEMINI_PCI_CTRL2 0x4C
-#define GEMINI_PCI_MEM1_BASE_SIZE 0x50
-#define GEMINI_PCI_MEM2_BASE_SIZE 0x54
-#define GEMINI_PCI_MEM3_BASE_SIZE 0x58
-
-#define PCI_CTRL2_INTSTS_OFFSET 28
-#define PCI_CTRL2_INTMASK_OFFSET 22
-
-#define GEMINI_PCI_DMA_MASK 0xFFF00000
-#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000
-#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000
-#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000
-#define GEMINI_PCI_DMA_MEM1_SIZE 7
-#define GEMINI_PCI_DMA_MEM2_SIZE 6
-#define GEMINI_PCI_DMA_MEM3_SIZE 6
-
-#define PCI_CONF_ENABLE (1 << 31)
-#define PCI_CONF_WHERE(r) ((r) & 0xFC)
-#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
-#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
-#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
-
-#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
-#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
-#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
-#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
-#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
-#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
-
-
-static DEFINE_SPINLOCK(gemini_pci_lock);
-
-static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
- int config, int size, u32* value)
-{
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-
- __raw_writel(PCI_CONF_BUS(bus->number) |
- PCI_CONF_DEVICE(PCI_SLOT(fn)) |
- PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
- PCI_CONF_WHERE(config) |
- PCI_CONF_ENABLE,
- PCI_CONFIG_REG);
-
- *value = __raw_readl(PCI_DATA_REG);
-
- if (size == 1)
- *value = (*value >> (8 * (config & 3))) & 0xFF;
- else if (size == 2)
- *value = (*value >> (8 * (config & 3))) & 0xFFFF;
-
- spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-
- dev_dbg(&bus->dev,
- "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
- PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
- int config, int size, u32 value)
-{
- unsigned long irq_flags = 0;
- int ret = PCIBIOS_SUCCESSFUL;
-
- dev_dbg(&bus->dev,
- "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
- PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
-
- spin_lock_irqsave(&gemini_pci_lock, irq_flags);
-
- __raw_writel(PCI_CONF_BUS(bus->number) |
- PCI_CONF_DEVICE(PCI_SLOT(fn)) |
- PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
- PCI_CONF_WHERE(config) |
- PCI_CONF_ENABLE,
- PCI_CONFIG_REG);
-
- switch(size) {
- case 4:
- __raw_writel(value, PCI_DATA_REG);
- break;
- case 2:
- __raw_writew(value, PCI_DATA_REG + (config & 3));
- break;
- case 1:
- __raw_writeb(value, PCI_DATA_REG + (config & 3));
- break;
- default:
- ret = PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
- spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
-
- return ret;
-}
-
-static struct pci_ops gemini_pci_ops = {
- .read = gemini_pci_read_config,
- .write = gemini_pci_write_config,
-};
-
-static struct resource gemini_pci_resource_io = {
- .name = "PCI I/O Space",
- .start = GEMINI_PCI_IO_BASE,
- .end = GEMINI_PCI_IO_BASE + SZ_1M - 1,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource gemini_pci_resource_mem = {
- .name = "PCI Memory Space",
- .start = GEMINI_PCI_MEM_BASE,
- .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
-{
- if (request_resource(&ioport_resource, &gemini_pci_resource_io))
- goto bad_resources;
- if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
- goto bad_resources;
-
- pci_add_resource(&sys->resources, &gemini_pci_resource_io);
- pci_add_resource(&sys->resources, &gemini_pci_resource_mem);
-
- return 0;
-
-bad_resources:
- pr_err("Gemini PCI: request_resource() failed. "
- "Abort PCI bus enumeration.\n");
- return -1;
-}
-
-static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
-{
- unsigned int cmd;
-
- pcibios_min_io = 0x100;
- pcibios_min_mem = 0;
-
- if ((nr > 0) || gemini_pci_request_resources(sys))
- return 0;
-
- /* setup I/O space to 1MB size */
- __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
-
- /* setup hostbridge */
- cmd = __raw_readl(PCI_CTRL_REG);
- cmd |= PCI_COMMAND_IO;
- cmd |= PCI_COMMAND_MEMORY;
- cmd |= PCI_COMMAND_MASTER;
- __raw_writel(cmd, PCI_CTRL_REG);
-
- return 1;
-}
-
-static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
-{
- unsigned int reg = 0;
- struct pci_bus* bus = 0;
-
- bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
- if (bus) {
- dev_dbg(&bus->dev, "setting up PCI DMA\n");
- reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
- | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
- gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
- reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
- | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
- gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
- reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
- | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
- gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
- }
-
- return bus;
-}
-
-/* Should work with all boards based on original Storlink EVB */
-static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if (slot < 9 || slot > 12)
- return -1;
-
- return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
-}
-
-static struct hw_pci gemini_hw_pci __initdata = {
- .nr_controllers = 1,
- .setup = gemini_pci_setup,
- .scan = gemini_pci_scan_bus,
- .map_irq = gemini_pci_map_irq,
-};
-
-/* we need this for muxed PCI interrupts handling */
-static struct pci_bus bogus_pci_bus;
-
-static void gemini_pci_ack_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- unsigned int reg;
-
- gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
- reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
- reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
- gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-}
-
-static void gemini_pci_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- unsigned int reg;
-
- gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
- reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
- | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
- gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-}
-
-static void gemini_pci_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- unsigned int reg;
-
- gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
- reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
- reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
- gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
-}
-
-static void gemini_pci_irq_handler(struct irq_desc *desc)
-{
- unsigned int pci_irq_no, irq_stat, reg, i;
-
- gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
- irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
-
- for (i = 0; i < 4; i++) {
-
- if ((irq_stat & (1 << i)) == 0)
- continue;
-
- pci_irq_no = PCI_IRQ_BASE + i;
-
- BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
- irq_desc[pci_irq_no].handle_irq(&irq_desc[pci_irq_no]);
- }
-}
-
-static struct irq_chip gemini_pci_irq_chip = {
- .name = "PCI",
- .irq_ack = gemini_pci_ack_irq,
- .irq_mask = gemini_pci_mask_irq,
- .irq_unmask = gemini_pci_unmask_irq,
-};
-
-static int __init gemini_pci_init(void)
-{
- int i;
-
- for (i = 72; i <= 95; i++)
- gpio_request(i, "PCI");
-
- /* initialize our bogus bus */
- dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
- bogus_pci_bus.number = 0;
-
- /* mask and clear all interrupts */
- gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
- 0xF000);
-
- for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
- irq_set_chip_and_handler(i, &gemini_pci_irq_chip,
- handle_level_irq);
- }
-
- irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
-
- pci_common_init(&gemini_hw_pci);
-
- return 0;
-}
-
-subsys_initcall(gemini_pci_init);
diff --git a/target/linux/gemini/files/drivers/ata/pata_gemini.c b/target/linux/gemini/files/drivers/ata/pata_gemini.c
deleted file mode 100644
index 707e8703bfc9..000000000000
--- a/target/linux/gemini/files/drivers/ata/pata_gemini.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Support for Gemini PATA
- *
- * Copyright (C) 2009 Janos Laube <***@gmail.com>
- * Copyright (C) 2010 Frederic Pecourt <***@free.fr>
- * Copyright (C) 2011 Tobias Waldvogel <***@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-/* Values of IOMUX
- * 26:24 bits is "IDE IO Select"
- * 111:100 - Reserved
- * 011 - ata0 <-> sata0, sata1; bring out ata1
- * 010 - ata1 <-> sata1, sata0; bring out ata0
- * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1
- * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/libata.h>
-#include <linux/leds.h>
-
-#include <mach/hardware.h>
-#include <mach/global_reg.h>
-
-#define DRV_NAME "pata-gemini"
-
-#define PATA_GEMINI_PORTS 1
-
-#define PIO_TIMING_REG 0x10
-#define MDMA_TIMING_REG 0x11
-#define UDMA_TIMING0_REG 0x12
-#define UDMA_TIMING1_REG 0x13
-#define CLK_MOD_REG 0x14
-
-#define CLK_MOD_66M_DEV0_BIT 0
-#define CLK_MOD_66M_DEV1_BIT 1
-#define CLK_MOD_UDMA_DEV0_BIT 4
-#define CLK_MOD_UDMA_DEV1_BIT 5
-
-#define CLK_MOD_66M_DEV0 (1 << CLK_MOD_66M_DEV0_BIT)
-#define CLK_MOD_66M_DEV1 (1 << CLK_MOD_66M_DEV1_BIT)
-#define CLK_MOD_UDMA_DEV0 (1 << CLK_MOD_UDMA_DEV0_BIT)
-#define CLK_MOD_UDMA_DEV1 (1 << CLK_MOD_UDMA_DEV1_BIT)
-
-#define SATA_ENABLE_PDEV_MASK 0x01
-#define SATA_ENABLE_PDEV_PM 0x02
-#define SATA_ENABLE_PDEV_ADDED 0x04
-#define SATA_ENABLE_PDEV_REMOVED 0x08
-#define SATA_ENABLE_SDEV_MASK 0x10
-#define SATA_ENABLE_SDEV_PM 0x20
-#define SATA_ENABLE_SDEV_ADDED 0x40
-#define SATA_ENABLE_SDEV_REMOVED 0x80
-
-MODULE_AUTHOR("Janos Laube <***@gmail.com>");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRV_NAME);
-
-static unsigned char PIO_TIMING[5] = {
- 0xaa, 0xa3, 0xa1, 0x33, 0x31
-};
-
-static unsigned char TIMING_MW_DMA[4][2] = {
- { 0x44, 1 }, // 480 4.2
- { 0x42, 1 }, // 150 13.3
- { 0x31, 1 }, // 120 16.7
- { 0x21, 1 }, // 100 20
-};
-
-static unsigned char TIMING_UDMA[7][2] = {
- { 0x33, 0 }, //240 16.7
- { 0x31, 0 }, //160 25
- { 0x21, 0 }, //120 33.3
- { 0x21, 1 }, //90 44.4
- { 0x11, 1 }, //60 66.7
- { 0x11 | 0x80, 0 }, //40 100
- { 0x11 | 0x80, 1 }, //30 133
-};
-
-static struct scsi_host_template pata_gemini_sht = {
- ATA_NCQ_SHT(DRV_NAME),
- .can_queue = 1,
- .sg_tablesize = 128,
- .dma_boundary = 0xffffU,
-};
-
-static void gemini_set_dmamode(struct ata_port *ap, struct ata_device *adev)
-{
- void __iomem *clk_reg = ap->ioaddr.bmdma_addr + CLK_MOD_REG;
- void __iomem *tim_reg = ap->ioaddr.bmdma_addr + UDMA_TIMING0_REG;
- unsigned short udma = adev->dma_mode;
- unsigned short speed = udma;
- unsigned short devno = adev->devno & 1;
- unsigned short i;
- u8 mod_udma_mask = 1 << (CLK_MOD_UDMA_DEV0_BIT + devno);
- u8 mod_66m_mask = 1 << (CLK_MOD_66M_DEV0_BIT + devno);
- u8 clk_mod;
- u8 timing;
-
- clk_mod = ioread8(clk_reg);
- clk_mod &= ~mod_udma_mask;
-
- if (speed & XFER_UDMA_0) {
- i = speed & ~XFER_UDMA_0;
- timing = TIMING_UDMA[i][0];
- clk_mod |= mod_udma_mask;
- if (TIMING_UDMA[i][1])
- clk_mod |= mod_66m_mask;
- } else {
- i = speed & ~XFER_MW_DMA_0;
- timing = TIMING_MW_DMA[i][0];
- clk_mod |= mod_udma_mask;
- if (TIMING_MW_DMA[i][1])
- clk_mod |= mod_66m_mask;
- }
-
- iowrite8(clk_mod, clk_reg);
- iowrite8(timing, tim_reg + devno);
- return;
-}
-
-static void gemini_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
- void __iomem *pio_reg = ap->ioaddr.bmdma_addr + PIO_TIMING_REG;
- unsigned int pio = adev->pio_mode - XFER_PIO_0;
-
- iowrite8(PIO_TIMING[pio], pio_reg);
-}
-
-unsigned int gemini_qc_issue(struct ata_queued_cmd *qc)
-{
- ledtrig_ide_activity();
- return ata_bmdma_qc_issue(qc);
-}
-
-static struct ata_port_operations pata_gemini_port_ops = {
- .inherits = &ata_bmdma_port_ops,
- .set_dmamode = gemini_set_dmamode,
- .set_piomode = gemini_set_piomode,
- .qc_issue = gemini_qc_issue,
-};
-
-static struct ata_port_info pata_gemini_portinfo = {
- .flags = 0,
- .udma_mask = ATA_UDMA6,
- .pio_mask = ATA_PIO4,
- .port_ops = &pata_gemini_port_ops,
-};
-
-static const struct ata_port_info *pata_gemini_ports = &pata_gemini_portinfo;
-
-static int pata_gemini_probe(struct platform_device *pdev)
-{
- struct ata_host *host;
- struct resource *res;
- unsigned int irq, i;
- void __iomem *mmio_base;
-
- /* standard bdma init */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-
- pr_info(DRV_NAME ": irq %d, io base 0x%08x\n", irq, res->start);
-
- mmio_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- host = ata_host_alloc_pinfo(&pdev->dev, &pata_gemini_ports, 1);
- if (!host)
- return -ENOMEM;
-
- for (i = 0; i < host->n_ports; i++) {
- struct ata_port *ap = host->ports[i];
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- ioaddr->bmdma_addr = mmio_base;
- ioaddr->cmd_addr = mmio_base + 0x20;
- ioaddr->ctl_addr = mmio_base + 0x36;
- ioaddr->altstatus_addr = ioaddr->ctl_addr;
- ata_sff_std_ports(ioaddr);
- host->ports[i]->cbl = ATA_CBL_SATA;
- }
-
- return ata_host_activate(host, irq, ata_bmdma_interrupt,
- IRQF_SHARED, &pata_gemini_sht);
-}
-
-static int pata_gemini_remove(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct ata_host *host = dev_get_drvdata(dev);
- ata_host_detach(host);
- return 0;
-}
-
-static struct platform_driver pata_gemini_driver = {
- .probe = pata_gemini_probe,
- .remove = pata_gemini_remove,
- .driver.owner = THIS_MODULE,
- .driver.name = DRV_NAME,
-};
-
-static int __init pata_gemini_module_init(void)
-{
- return platform_driver_probe(&pata_gemini_driver, pata_gemini_probe);
-}
-
-static void __exit pata_gemini_module_exit(void)
-{
- platform_driver_unregister(&pata_gemini_driver);
-}
-
-module_init(pata_gemini_module_init);
-module_exit(pata_gemini_module_exit);
diff --git a/target/linux/gemini/files/drivers/net/ethernet/gemini/Kconfig b/target/linux/gemini/files/drivers/net/ethernet/gemini/Kconfig
deleted file mode 100644
index 12d58163d00d..000000000000
--- a/target/linux/gemini/files/drivers/net/ethernet/gemini/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Gemini device configuration
-#
-
-config NET_VENDOR_GEMINI
- bool "Cortina Gemini devices"
- default y
- depends on ARCH_GEMINI
- ---help---
- If you have a network (Ethernet) card belonging to this class, say Y
- and read the Ethernet-HOWTO, available from
- <http://www.tldp.org/docs.html#howto>.
-
- Note that the answer to this question doesn't directly affect the
- kernel: saying N will just cause the configurator to skip all
- the questions about D-Link devices. If you say Y, you will be asked for
- your specific card in the following questions.
-
-if NET_VENDOR_GEMINI
-
-config GEMINI_SL351X
- tristate "StorLink SL351x Gigabit Ethernet support"
- depends on ARCH_GEMINI
- select PHYLIB
- select MDIO_BITBANG
- select MDIO_GPIO
- select CRC32
- ---help---
- This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
-
-endif # NET_VENDOR_GEMINI
diff --git a/target/linux/gemini/files/drivers/net/ethernet/gemini/Makefile b/target/linux/gemini/files/drivers/net/ethernet/gemini/Makefile
deleted file mode 100644
index 3a1987c4fa42..000000000000
--- a/target/linux/gemini/files/drivers/net/ethernet/gemini/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Cortina Gemini network device drivers.
-#
-
-obj-$(CONFIG_GEMINI_SL351X) += sl351x.o
diff --git a/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x.c b/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x.c
deleted file mode 100644
index 83455c400319..000000000000
--- a/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x.c
+++ /dev/null
@@ -1,2340 +0,0 @@
-/*
- * Ethernet device driver for Gemini SoC (SL351x GMAC).
- *
- * Copyright (C) 2011, Tobias Waldvogel <***@gmail.com>
- *
- * Based on work by Michał Mirosław <mirq-***@rere.qmqm.pl> and
- * Paulius Zaleckas <***@gmail.com> and
- * Giuseppe De Robertis <***@ba.infn.it> and
- * GPLd spaghetti code from Raidsonic and other Gemini-based NAS vendors.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-#include <linux/cache.h>
-#include <linux/interrupt.h>
-
-#include <linux/platform_device.h>
-#include <linux/etherdevice.h>
-#include <linux/if_vlan.h>
-#include <linux/skbuff.h>
-#include <linux/phy.h>
-#include <linux/crc32.h>
-#include <linux/ethtool.h>
-#include <linux/tcp.h>
-#include <linux/u64_stats_sync.h>
-
-#include <linux/in.h>
-#include <linux/ip.h>
-#include <linux/ipv6.h>
-
-#include <mach/hardware.h>
-#include <mach/global_reg.h>
-
-#include <mach/gmac.h>
-#include "sl351x_hw.h"
-
-#define DRV_NAME "gmac-gemini"
-#define DRV_VERSION "1.0"
-
-#define HSIZE_8 0b00
-#define HSIZE_16 0b01
-#define HSIZE_32 0b10
-
-#define HBURST_SINGLE 0b00
-#define HBURST_INCR 0b01
-#define HBURST_INCR4 0b10
-#define HBURST_INCR8 0b11
-
-#define HPROT_DATA_CACHE BIT(0)
-#define HPROT_PRIVILIGED BIT(1)
-#define HPROT_BUFFERABLE BIT(2)
-#define HPROT_CACHABLE BIT(3)
-
-#define DEFAULT_RX_COALESCE_NSECS 0
-#define DEFAULT_GMAC_RXQ_ORDER 9
-#define DEFAULT_GMAC_TXQ_ORDER 8
-#define DEFAULT_RX_BUF_ORDER 11
-#define DEFAULT_NAPI_WEIGHT 64
-#define TX_MAX_FRAGS 16
-#define TX_QUEUE_NUM 1 /* max: 6 */
-#define RX_MAX_ALLOC_ORDER 2
-
-#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \
- GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT)
-#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT| \
- GMAC0_SWTQ00_FIN_INT_BIT)
-#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT|GMAC0_RX_OVERRUN_INT_BIT)
-
-#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
- NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
- NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
-
-MODULE_AUTHOR("Tobias Waldvogel");
-MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRV_NAME);
-
-struct toe_private {
- void __iomem *iomem;
- spinlock_t irq_lock;
-
- struct net_device *netdev[2];
- __le32 mac_addr[2][3];
-
- struct device *dev;
- int irq;
-
- unsigned int freeq_order;
- unsigned int freeq_frag_order;
- GMAC_RXDESC_T *freeq_ring;
- dma_addr_t freeq_dma_base;
- struct page **freeq_page_tab;
- spinlock_t freeq_lock;
-};
-
-struct gmac_txq {
- GMAC_TXDESC_T *ring;
- struct sk_buff **skb;
- unsigned int cptr;
- unsigned int noirq_packets;
-};
-
-struct gmac_private {
- unsigned int num;
- struct toe_private *toe;
- void __iomem *ctl_iomem;
- void __iomem *dma_iomem;
-
- void __iomem *rxq_rwptr;
- GMAC_RXDESC_T *rxq_ring;
- unsigned int rxq_order;
-
- struct napi_struct napi;
- struct hrtimer rx_coalesce_timer;
- unsigned int rx_coalesce_nsecs;
- unsigned int freeq_refill;
- struct gmac_txq txq[TX_QUEUE_NUM];
- unsigned int txq_order;
- unsigned int irq_every_tx_packets;
-
- dma_addr_t rxq_dma_base;
- dma_addr_t txq_dma_base;
-
- unsigned int msg_enable;
- spinlock_t config_lock;
-
- struct u64_stats_sync tx_stats_syncp;
- struct u64_stats_sync rx_stats_syncp;
- struct u64_stats_sync ir_stats_syncp;
-
- struct rtnl_link_stats64 stats;
- u64 hw_stats[RX_STATS_NUM];
- u64 rx_stats[RX_STATUS_NUM];
- u64 rx_csum_stats[RX_CHKSUM_NUM];
- u64 rx_napi_exits;
- u64 tx_frag_stats[TX_MAX_FRAGS];
- u64 tx_frags_linearized;
- u64 tx_hw_csummed;
-};
-
-#define GMAC_STATS_NUM ( \
- RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
- TX_MAX_FRAGS + 2)
-
-static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
- "GMAC_IN_DISCARDS",
- "GMAC_IN_ERRORS",
- "GMAC_IN_MCAST",
- "GMAC_IN_BCAST",
- "GMAC_IN_MAC1",
- "GMAC_IN_MAC2",
- "RX_STATUS_GOOD_FRAME",
- "RX_STATUS_TOO_LONG_GOOD_CRC",
- "RX_STATUS_RUNT_FRAME",
- "RX_STATUS_SFD_NOT_FOUND",
- "RX_STATUS_CRC_ERROR",
- "RX_STATUS_TOO_LONG_BAD_CRC",
- "RX_STATUS_ALIGNMENT_ERROR",
- "RX_STATUS_TOO_LONG_BAD_ALIGN",
- "RX_STATUS_RX_ERR",
- "RX_STATUS_DA_FILTERED",
- "RX_STATUS_BUFFER_FULL",
- "RX_STATUS_11",
- "RX_STATUS_12",
- "RX_STATUS_13",
- "RX_STATUS_14",
- "RX_STATUS_15",
- "RX_CHKSUM_IP_UDP_TCP_OK",
- "RX_CHKSUM_IP_OK_ONLY",
- "RX_CHKSUM_NONE",
- "RX_CHKSUM_3",
- "RX_CHKSUM_IP_ERR_UNKNOWN",
- "RX_CHKSUM_IP_ERR",
- "RX_CHKSUM_TCP_UDP_ERR",
- "RX_CHKSUM_7",
- "RX_NAPI_EXITS",
- "TX_FRAGS[1]",
- "TX_FRAGS[2]",
- "TX_FRAGS[3]",
- "TX_FRAGS[4]",
- "TX_FRAGS[5]",
- "TX_FRAGS[6]",
- "TX_FRAGS[7]",
- "TX_FRAGS[8]",
- "TX_FRAGS[9]",
- "TX_FRAGS[10]",
- "TX_FRAGS[11]",
- "TX_FRAGS[12]",
- "TX_FRAGS[13]",
- "TX_FRAGS[14]",
- "TX_FRAGS[15]",
- "TX_FRAGS[16+]",
- "TX_FRAGS_LINEARIZED",
- "TX_HW_CSUMMED",
-};
-
-static void gmac_dump_dma_state(struct net_device *dev);
-
-static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&gmac->config_lock, flags);
-
- reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
- reg = (reg & ~vmask) | val;
- writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
-
- spin_unlock_irqrestore(&gmac->config_lock, flags);
-}
-
-static void gmac_enable_tx_rx(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&gmac->config_lock, flags);
-
- reg = readl(config0);
- reg &= ~CONFIG0_TX_RX_DISABLE;
- writel(reg, config0);
-
- spin_unlock_irqrestore(&gmac->config_lock, flags);
-}
-
-static void gmac_disable_tx_rx(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&gmac->config_lock, flags);
-
- reg = readl(config0);
- reg |= CONFIG0_TX_RX_DISABLE;
- writel(reg, config0);
-
- spin_unlock_irqrestore(&gmac->config_lock, flags);
-
- mdelay(10); /* let GMAC consume packet */
-}
-
-static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&gmac->config_lock, flags);
-
- reg = readl(config0);
- reg &= ~CONFIG0_FLOW_CTL;
- if (tx)
- reg |= CONFIG0_FLOW_TX;
- if (rx)
- reg |= CONFIG0_FLOW_RX;
- writel(reg, config0);
-
- spin_unlock_irqrestore(&gmac->config_lock, flags);
-}
-
-static void gmac_update_link_state(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- void __iomem *status_reg = gmac->ctl_iomem + GMAC_STATUS;
- struct phy_device *phydev = dev->phydev;
- GMAC_STATUS_T status, old_status;
- int pause_tx=0, pause_rx=0;
-
- old_status.bits32 = status.bits32 = readl(status_reg);
-
- status.bits.link = phydev->link;
- status.bits.duplex = phydev->duplex;
-
- switch (phydev->speed) {
- case 1000:
- status.bits.speed = GMAC_SPEED_1000;
- if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
- status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
- break;
- case 100:
- status.bits.speed = GMAC_SPEED_100;
- if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
- status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
- break;
- case 10:
- status.bits.speed = GMAC_SPEED_10;
- if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
- status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
- break;
- default:
- netdev_warn(dev, "Not supported PHY speed (%d)\n",
- phydev->speed);
- }
-
- if (phydev->duplex == DUPLEX_FULL) {
- u16 lcladv = phy_read(phydev, MII_ADVERTISE);
- u16 rmtadv = phy_read(phydev, MII_LPA);
- u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
-
- if (cap & FLOW_CTRL_RX)
- pause_rx=1;
- if (cap & FLOW_CTRL_TX)
- pause_tx=1;
- }
-
- gmac_set_flow_control(dev, pause_tx, pause_rx);
-
- if (old_status.bits32 == status.bits32)
- return;
-
- if (netif_msg_link(gmac)) {
- phy_print_status(phydev);
- netdev_info(dev, "link flow control: %s\n",
- phydev->pause
- ? (phydev->asym_pause ? "tx" : "both")
- : (phydev->asym_pause ? "rx" : "none")
- );
- }
-
- gmac_disable_tx_rx(dev);
- writel(status.bits32, status_reg);
- gmac_enable_tx_rx(dev);
-}
-
-static int gmac_setup_phy(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- struct gemini_gmac_platform_data *pdata = toe->dev->platform_data;
- GMAC_STATUS_T status = { .bits32 = 0 };
- int num = dev->dev_id;
-
- dev->phydev = phy_connect(dev, pdata->bus_id[num],
- &gmac_update_link_state, pdata->interface[num]);
-
- if (IS_ERR(dev->phydev)) {
- int err = PTR_ERR(dev->phydev);
- dev->phydev = NULL;
- return err;
- }
-
- dev->phydev->supported &= PHY_GBIT_FEATURES;
- dev->phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
- dev->phydev->advertising = dev->phydev->supported;
-
- /* set PHY interface type */
- switch (dev->phydev->interface) {
- case PHY_INTERFACE_MODE_MII:
- status.bits.mii_rmii = GMAC_PHY_MII;
- break;
- case PHY_INTERFACE_MODE_GMII:
- status.bits.mii_rmii = GMAC_PHY_GMII;
- break;
- case PHY_INTERFACE_MODE_RGMII:
- status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
- break;
- default:
- netdev_err(dev, "Unsupported MII interface\n");
- phy_disconnect(dev->phydev);
- dev->phydev = NULL;
- return -EINVAL;
- }
- writel(status.bits32, gmac->ctl_iomem + GMAC_STATUS);
-
- return 0;
-}
-
-static int gmac_pick_rx_max_len(int max_l3_len)
-{
- /* index = CONFIG_MAXLEN_XXX values */
- static const int max_len[8] = {
- 1536, 1518, 1522, 1542,
- 9212, 10236, 1518, 1518
- };
- int i, n = 5;
-
- max_l3_len += ETH_HLEN + VLAN_HLEN;
-
- if (max_l3_len > max_len[n])
- return -1;
-
- for (i = 0; i < 5; ++i) {
- if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
- n = i;
- }
-
- return n;
-}
-
-static int gmac_init(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- u32 val;
-
- GMAC_CONFIG0_T config0 = { .bits = {
- .dis_tx = 1,
- .dis_rx = 1,
- .ipv4_rx_chksum = 1,
- .ipv6_rx_chksum = 1,
- .rx_err_detect = 1,
- .rgmm_edge = 1,
- .port0_chk_hwq = 1,
- .port1_chk_hwq = 1,
- .port0_chk_toeq = 1,
- .port1_chk_toeq = 1,
- .port0_chk_classq = 1,
- .port1_chk_classq = 1,
- } };
- GMAC_AHB_WEIGHT_T ahb_weight = { .bits = {
- .rx_weight = 1,
- .tx_weight = 1,
- .hash_weight = 1,
- .pre_req = 0x1f,
- .tqDV_threshold = 0,
- } };
- GMAC_TX_WCR0_T hw_weigh = { .bits = {
- .hw_tq3 = 1,
- .hw_tq2 = 1,
- .hw_tq1 = 1,
- .hw_tq0 = 1,
- } };
- GMAC_TX_WCR1_T sw_weigh = { .bits = {
- .sw_tq5 = 1,
- .sw_tq4 = 1,
- .sw_tq3 = 1,
- .sw_tq2 = 1,
- .sw_tq1 = 1,
- .sw_tq0 = 1,
- } };
- GMAC_CONFIG1_T config1 = { .bits = {
- .set_threshold = 16,
- .rel_threshold = 24,
- } };
- GMAC_CONFIG2_T config2 = { .bits = {
- .set_threshold = 16,
- .rel_threshold = 32,
- } };
- GMAC_CONFIG3_T config3 = { .bits = {
- .set_threshold = 0,
- .rel_threshold = 0,
- } };
-
- config0.bits.max_len = gmac_pick_rx_max_len(dev->mtu);
-
- val = readl(gmac->ctl_iomem + GMAC_CONFIG0);
- config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved;
- writel(config0.bits32, gmac->ctl_iomem + GMAC_CONFIG0);
- writel(config1.bits32, gmac->ctl_iomem + GMAC_CONFIG1);
- writel(config2.bits32, gmac->ctl_iomem + GMAC_CONFIG2);
- writel(config3.bits32, gmac->ctl_iomem + GMAC_CONFIG3);
-
- val = readl(gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
- writel(ahb_weight.bits32, gmac->dma_iomem + GMAC_AHB_WEIGHT_REG);
-
- writel(hw_weigh.bits32,
- gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_0_REG);
- writel(sw_weigh.bits32,
- gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_1_REG);
-
- gmac->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
- gmac->txq_order = DEFAULT_GMAC_TXQ_ORDER;
- gmac->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
-
- /* Mark every quarter of the queue a packet for interrupt
- in order to be able to wake up the queue if it was stopped */
- gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
-
- return 0;
-}
-
-static void gmac_uninit(struct net_device *dev)
-{
- if (dev->phydev)
- phy_disconnect(dev->phydev);
-}
-
-static int gmac_setup_txqs(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
- void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
-
- unsigned int n_txq = dev->num_tx_queues;
- size_t entries = 1 <<gmac->txq_order;
- size_t len = n_txq * entries;
- struct gmac_txq *txq = gmac->txq;
- GMAC_TXDESC_T *desc_ring;
- struct sk_buff **skb_tab;
- unsigned int r;
- int i;
-
- skb_tab = kzalloc(len * sizeof(*skb_tab), GFP_KERNEL);
- if (!skb_tab)
- return -ENOMEM;
-
- desc_ring = dma_alloc_coherent(toe->dev, len * sizeof(*desc_ring),
- &gmac->txq_dma_base, GFP_KERNEL);
-
- if (!desc_ring) {
- kfree(skb_tab);
- return -ENOMEM;
- }
-
- BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK);
-
- writel(gmac->txq_dma_base | gmac->txq_order, base_reg);
-
- for (i = 0; i < n_txq; i++) {
- txq->ring = desc_ring;
- txq->skb = skb_tab;
- txq->noirq_packets = 0;
-
- r = readw(rwptr_reg);
- rwptr_reg += 2;
- writew(r, rwptr_reg);
- rwptr_reg +=2;
- txq->cptr = r;
-
- txq++;
- desc_ring += entries;
- skb_tab += entries;
- }
-
- return 0;
-}
-
-static void gmac_clean_txq(struct net_device *dev, struct gmac_txq *txq,
- unsigned int r)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned int errs = 0;
- unsigned int pkts = 0;
- unsigned int hwchksum = 0;
- unsigned long bytes = 0;
- unsigned int m = (1 << gmac->txq_order) - 1;
- unsigned int c = txq->cptr;
- GMAC_TXDESC_0_T word0;
- GMAC_TXDESC_1_T word1;
- unsigned int word3;
- dma_addr_t mapping;
- GMAC_TXDESC_T *txd;
- unsigned short nfrags;
-
- if (unlikely(c == r))
- return;
-
- rmb();
- while (c != r) {
- txd = txq->ring + c;
- word0 = txd->word0;
- word1 = txd->word1;
- mapping = txd->word2.buf_adr;
- word3 = txd->word3.bits32;
-
- dma_unmap_single(toe->dev, mapping, word0.bits.buffer_size, DMA_TO_DEVICE);
-
- if (word3 & EOF_BIT)
- dev_kfree_skb(txq->skb[c]);
-
- c++;
- c &= m;
-
- if (!(word3 & SOF_BIT))
- continue;
-
- if (!word0.bits.status_tx_ok) {
- errs++;
- continue;
- }
-
- pkts++;
- bytes += txd->word1.bits.byte_count;
-
- if (word1.bits32 & TSS_CHECKUM_ENABLE)
- hwchksum++;
-
- nfrags = word0.bits.desc_count - 1;
- if (nfrags) {
- if (nfrags >= TX_MAX_FRAGS)
- nfrags = TX_MAX_FRAGS - 1;
-
- u64_stats_update_begin(&gmac->tx_stats_syncp);
- gmac->tx_frag_stats[nfrags]++;
- u64_stats_update_end(&gmac->ir_stats_syncp);
- }
- }
-
- u64_stats_update_begin(&gmac->ir_stats_syncp);
- gmac->stats.tx_errors += errs;
- gmac->stats.tx_packets += pkts;
- gmac->stats.tx_bytes += bytes;
- gmac->tx_hw_csummed += hwchksum;
- u64_stats_update_end(&gmac->ir_stats_syncp);
-
- txq->cptr = c;
-}
-
-static void gmac_cleanup_txqs(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
- void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG;
-
- unsigned n_txq = dev->num_tx_queues;
- unsigned int r, i;
-
- for (i = 0; i < n_txq; i++) {
- r = readw(rwptr_reg);
- rwptr_reg += 2;
- writew(r, rwptr_reg);
- rwptr_reg += 2;
-
- gmac_clean_txq(dev, gmac->txq + i, r);
- }
- writel(0, base_reg);
-
- kfree(gmac->txq->skb);
- dma_free_coherent(toe->dev,
- n_txq * sizeof(*gmac->txq->ring) << gmac->txq_order,
- gmac->txq->ring, gmac->txq_dma_base);
-}
-
-static int gmac_setup_rxq(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
-
- gmac->rxq_rwptr = &qhdr->word1;
- gmac->rxq_ring = dma_alloc_coherent(toe->dev,
- sizeof(*gmac->rxq_ring) << gmac->rxq_order,
- &gmac->rxq_dma_base, GFP_KERNEL);
- if (!gmac->rxq_ring)
- return -ENOMEM;
-
- BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK);
-
- writel(gmac->rxq_dma_base | gmac->rxq_order, &qhdr->word0);
- writel(0, gmac->rxq_rwptr);
- return 0;
-}
-
-static void gmac_cleanup_rxq(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
-
- NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id);
- void __iomem *dma_reg = &qhdr->word0;
- void __iomem *ptr_reg = &qhdr->word1;
- GMAC_RXDESC_T *rxd = gmac->rxq_ring;
- DMA_RWPTR_T rw;
- unsigned int r, w;
- unsigned int m = (1 <<gmac->rxq_order) - 1;
- struct page *page;
- dma_addr_t mapping;
-
- rw.bits32 = readl(ptr_reg);
- r = rw.bits.rptr;
- w = rw.bits.wptr;
- writew(r, ptr_reg + 2);
-
- writel(0, dma_reg);
-
- rmb();
- while (r != w) {
- mapping = rxd[r].word2.buf_adr;
- r++;
- r &= m;
-
- if (!mapping)
- continue;
-
- page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
- put_page(page);
- }
-
- dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_order,
- gmac->rxq_ring, gmac->rxq_dma_base);
-}
-
-static struct page *toe_freeq_alloc_map_page(struct toe_private *toe, int pn)
-{
- unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
- unsigned int frag_len = 1 << toe->freeq_frag_order;
- GMAC_RXDESC_T *freeq_entry;
- dma_addr_t mapping;
- struct page *page;
- int i;
-
- page = alloc_page(__GFP_COLD | GFP_ATOMIC);
- if (!page)
- return NULL;
-
- mapping = dma_map_single(toe->dev, page_address(page),
- PAGE_SIZE, DMA_FROM_DEVICE);
-
- if (unlikely(dma_mapping_error(toe->dev, mapping) || !mapping)) {
- put_page(page);
- return NULL;
- }
-
- freeq_entry = toe->freeq_ring + (pn << fpp_order);
- for (i = 1 << fpp_order; i > 0; --i) {
- freeq_entry->word2.buf_adr = mapping;
- freeq_entry++;
- mapping += frag_len;
- }
-
- if (toe->freeq_page_tab[pn]) {
- mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
- dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
- put_page(toe->freeq_page_tab[pn]);
- }
-
- toe->freeq_page_tab[pn] = page;
- return page;
-}
-
-static unsigned int toe_fill_freeq(struct toe_private *toe, int reset)
-{
- void __iomem *rwptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
-
- DMA_RWPTR_T rw;
- unsigned int pn, epn;
- unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
- unsigned int m_pn = (1 << (toe->freeq_order - fpp_order)) - 1;
- struct page *page;
- unsigned int count = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&toe->freeq_lock, flags);
-
- rw.bits32 = readl(rwptr_reg);
- pn = (reset ? rw.bits.rptr : rw.bits.wptr) >> fpp_order;
- epn = (rw.bits.rptr >> fpp_order) - 1;
- epn &= m_pn;
-
- while (pn != epn) {
- page = toe->freeq_page_tab[pn];
-
- if (atomic_read(&page->_count) > 1) {
- unsigned int fl = (pn -epn) & m_pn;
-
- if (fl > 64 >> fpp_order)
- break;
-
- page = toe_freeq_alloc_map_page(toe, pn);
- if (!page)
- break;
- }
-
- atomic_add(1 << fpp_order, &page->_count);
- count += 1 << fpp_order;
- pn++;
- pn &= m_pn;
- }
-
- wmb();
- writew(pn << fpp_order, rwptr_reg+2);
-
- spin_unlock_irqrestore(&toe->freeq_lock, flags);
- return count;
-}
-
-static int toe_setup_freeq(struct toe_private *toe)
-{
- void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
- QUEUE_THRESHOLD_T qt;
- DMA_SKB_SIZE_T skbsz;
- unsigned int filled;
- unsigned int frag_len = 1 << toe->freeq_frag_order;
- unsigned int len = 1 << toe->freeq_order;
- unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
- unsigned int pages = len >> fpp_order;
- dma_addr_t mapping;
- unsigned int pn;
-
- toe->freeq_ring = dma_alloc_coherent(toe->dev,
- sizeof(*toe->freeq_ring) << toe->freeq_order,
- &toe->freeq_dma_base, GFP_KERNEL);
- if (!toe->freeq_ring)
- return -ENOMEM;
-
- BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK);
-
- toe->freeq_page_tab = kzalloc(pages * sizeof(*toe->freeq_page_tab),
- GFP_KERNEL);
- if (!toe->freeq_page_tab)
- goto err_freeq;
-
- for (pn = 0; pn < pages; pn++)
- if (!toe_freeq_alloc_map_page(toe, pn))
- goto err_freeq_alloc;
-
- filled = toe_fill_freeq(toe, 1);
- if (!filled)
- goto err_freeq_alloc;
-
- qt.bits32 = readl(toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
- qt.bits.swfq_empty = 32;
- writel(qt.bits32, toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG);
-
- skbsz.bits.sw_skb_size = 1 << toe->freeq_frag_order;
- writel(skbsz.bits32, toe->iomem + GLOBAL_DMA_SKB_SIZE_REG);
- writel(toe->freeq_dma_base | toe->freeq_order, dma_reg);
-
- return 0;
-
-err_freeq_alloc:
- while (pn > 0) {
- --pn;
- mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
- dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
- put_page(toe->freeq_page_tab[pn]);
- }
-
-err_freeq:
- dma_free_coherent(toe->dev,
- sizeof(*toe->freeq_ring) << toe->freeq_order,
- toe->freeq_ring, toe->freeq_dma_base);
- toe->freeq_ring = NULL;
- return -ENOMEM;
-}
-
-static void toe_cleanup_freeq(struct toe_private *toe)
-{
- void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG;
- void __iomem *ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
-
- unsigned int frag_len = 1 << toe->freeq_frag_order;
- unsigned int len = 1 << toe->freeq_order;
- unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order;
- unsigned int pages = len >> fpp_order;
- struct page *page;
- dma_addr_t mapping;
- unsigned int pn;
-
- writew(readw(ptr_reg), ptr_reg + 2);
- writel(0, dma_reg);
-
- for (pn = 0; pn < pages; pn++) {
- mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr;
- dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE);
-
- page = toe->freeq_page_tab[pn];
- while (atomic_read(&page->_count) > 0)
- put_page(page);
- }
-
- kfree(toe->freeq_page_tab);
-
- dma_free_coherent(toe->dev,
- sizeof(*toe->freeq_ring) << toe->freeq_order,
- toe->freeq_ring, toe->freeq_dma_base);
-}
-
-static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id)
-{
- void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
- struct gmac_private *gmac;
- struct net_device *other = toe->netdev[1 - changing_dev_id];
- unsigned new_size = 0;
- unsigned new_order;
- int err;
- unsigned long flags;
- unsigned en;
-
- if (other && netif_running(other))
- return -EBUSY;
-
- if (toe->netdev[0]) {
- gmac = netdev_priv(toe->netdev[0]);
- new_size = 1 << (gmac->rxq_order + 1);
- }
-
- if (toe->netdev[1]) {
- gmac = netdev_priv(toe->netdev[1]);
- new_size += 1 << (gmac->rxq_order + 1);
- }
-
- new_order = min(15, ilog2(new_size - 1) + 1);
- if (toe->freeq_order == new_order)
- return 0;
-
- spin_lock_irqsave(&toe->irq_lock, flags);
- en = readl(irqen_reg);
- en &= ~SWFQ_EMPTY_INT_BIT;
- writel(en, irqen_reg);
-
- if (toe->freeq_ring)
- toe_cleanup_freeq(toe);
-
- toe->freeq_order = new_order;
- err = toe_setup_freeq(toe);
-
- en |= SWFQ_EMPTY_INT_BIT;
- writel(en, irqen_reg);
- spin_unlock_irqrestore(&toe->irq_lock, flags);
-
- return err;
-}
-
-static void gmac_tx_irq_enable(struct net_device *dev, unsigned txq, int en)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned val, mask;
-
- mask = GMAC0_IRQ0_TXQ0_INTS << (6 * dev->dev_id + txq);
-
- if (en)
- writel(mask, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
-
- val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
- val = en ? val | mask : val & ~mask;
- writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
-}
-
-
-static void gmac_tx_irq(struct net_device *dev, unsigned txq_num)
-{
- struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num);
-
- gmac_tx_irq_enable(dev, txq_num, 0);
- netif_tx_wake_queue(ntxq);
-}
-
-static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb,
- struct gmac_txq *txq, unsigned short *desc)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- struct skb_shared_info *skb_si = skb_shinfo(skb);
- skb_frag_t *skb_frag;
- short frag, last_frag = skb_si->nr_frags - 1;
- unsigned short m = (1 << gmac->txq_order) -1;
- unsigned short w = *desc;
- unsigned word1, word3, buflen;
- dma_addr_t mapping;
- void *buffer;
- unsigned short mtu;
- GMAC_TXDESC_T *txd;
-
- mtu = ETH_HLEN;
- mtu += dev->mtu;
- if (skb->protocol == htons(ETH_P_8021Q))
- mtu += VLAN_HLEN;
-
- word1 = skb->len;
- word3 = SOF_BIT;
-
- if (word1 > mtu) {
- word1 |= TSS_MTU_ENABLE_BIT;
- word3 += mtu;
- }
-
- if (skb->ip_summed != CHECKSUM_NONE) {
- int tcp = 0;
- if (skb->protocol == htons(ETH_P_IP)) {
- word1 |= TSS_IP_CHKSUM_BIT;
- tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
- } else { /* IPv6 */
- word1 |= TSS_IPV6_ENABLE_BIT;
- tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
- }
-
- word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
- }
-
- frag = -1;
- while (frag <= last_frag) {
- if (frag == -1) {
- buffer = skb->data;
- buflen = skb_headlen(skb);
- } else {
- skb_frag = skb_si->frags + frag;
- buffer = page_address(skb_frag_page(skb_frag)) +
- skb_frag->page_offset;
- buflen = skb_frag->size;
- }
-
- if (frag == last_frag) {
- word3 |= EOF_BIT;
- txq->skb[w] = skb;
- }
-
- mapping = dma_map_single(toe->dev, buffer, buflen,
- DMA_TO_DEVICE);
- if (dma_mapping_error(toe->dev, mapping) ||
- !(mapping & PAGE_MASK))
- goto map_error;
-
- txd = txq->ring + w;
- txd->word0.bits32 = buflen;
- txd->word1.bits32 = word1;
- txd->word2.buf_adr = mapping;
- txd->word3.bits32 = word3;
-
- word3 &= MTU_SIZE_BIT_MASK;
- w++;
- w &= m;
- frag++;
- }
-
- *desc = w;
- return 0;
-
-map_error:
- while (w != *desc) {
- w--;
- w &= m;
-
- dma_unmap_page(toe->dev, txq->ring[w].word2.buf_adr,
- txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE);
- }
- return ENOMEM;
-}
-
-static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
-
- void __iomem *ptr_reg;
- struct gmac_txq *txq;
- struct netdev_queue *ntxq;
- int txq_num, nfrags;
- DMA_RWPTR_T rw;
- unsigned short r, w, d;
- unsigned short m = (1 << gmac->txq_order) - 1;
-
- SKB_FRAG_ASSERT(skb);
-
- if (unlikely(skb->len >= 0x10000))
- goto out_drop_free;
-
- txq_num = skb_get_queue_mapping(skb);
- ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
- txq = &gmac->txq[txq_num];
- ntxq = netdev_get_tx_queue(dev, txq_num);
- nfrags = skb_shinfo(skb)->nr_frags;
-
- rw.bits32 = readl(ptr_reg);
- r = rw.bits.rptr;
- w = rw.bits.wptr;
-
- d = txq->cptr - w - 1;
- d &= m;
-
- if (unlikely(d < nfrags+2))
- {
- gmac_clean_txq(dev, txq, r);
- d = txq->cptr - w - 1;
- d &= m;
-
- if (unlikely(d < nfrags+2)) {
- netif_tx_stop_queue(ntxq);
-
- d = txq->cptr + nfrags + 16;
- d &= m;
- txq->ring[d].word3.bits.eofie = 1;
- gmac_tx_irq_enable(dev, txq_num, 1);
-
- u64_stats_update_begin(&gmac->tx_stats_syncp);
- dev->stats.tx_fifo_errors++;
- u64_stats_update_end(&gmac->tx_stats_syncp);
- return NETDEV_TX_BUSY;
- }
- }
-
- if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) {
- if (skb_linearize(skb))
- goto out_drop;
-
- if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w)))
- goto out_drop_free;
-
- u64_stats_update_begin(&gmac->tx_stats_syncp);
- gmac->tx_frags_linearized++;
- u64_stats_update_end(&gmac->tx_stats_syncp);
- }
-
- writew(w, ptr_reg+2);
-
- gmac_clean_txq(dev, txq, r);
- return NETDEV_TX_OK;
-
-out_drop_free:
- dev_kfree_skb(skb);
-out_drop:
- u64_stats_update_begin(&gmac->tx_stats_syncp);
- gmac->stats.tx_dropped++;
- u64_stats_update_end(&gmac->tx_stats_syncp);
- return NETDEV_TX_OK;
-}
-
-static void gmac_tx_timeout(struct net_device *dev)
-{
- netdev_err(dev, "Tx timeout\n");
- gmac_dump_dma_state(dev);
-}
-
-static void gmac_enable_irq(struct net_device *dev, int enable)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned long flags;
- unsigned val, mask;
-
- spin_lock_irqsave(&toe->irq_lock, flags);
-
- mask = GMAC0_IRQ0_2 << (dev->dev_id * 2);
- val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
- val = enable ? (val | mask) : (val & ~mask);
- writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
-
- mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
- val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
- val = enable ? (val | mask) : (val & ~mask);
- writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
-
- mask = GMAC0_IRQ4_8 << (dev->dev_id * 8);
- val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
- val = enable ? (val | mask) : (val & ~mask);
- writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
-
- spin_unlock_irqrestore(&toe->irq_lock, flags);
-}
-
-static void gmac_enable_rx_irq(struct net_device *dev, int enable)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned long flags;
- unsigned val, mask;
-
- spin_lock_irqsave(&toe->irq_lock, flags);
- mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
-
- val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
- val = enable ? (val | mask) : (val & ~mask);
- writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
-
- spin_unlock_irqrestore(&toe->irq_lock, flags);
-}
-
-static struct sk_buff *gmac_skb_if_good_frame(struct gmac_private *gmac,
- GMAC_RXDESC_0_T word0, unsigned frame_len)
-{
- struct sk_buff *skb = NULL;
- unsigned rx_status = word0.bits.status;
- unsigned rx_csum = word0.bits.chksum_status;
-
- gmac->rx_stats[rx_status]++;
- gmac->rx_csum_stats[rx_csum]++;
-
- if (word0.bits.derr || word0.bits.perr ||
- rx_status || frame_len < ETH_ZLEN ||
- rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
- gmac->stats.rx_errors++;
-
- if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
- gmac->stats.rx_length_errors++;
- if (RX_ERROR_OVER(rx_status))
- gmac->stats.rx_over_errors++;
- if (RX_ERROR_CRC(rx_status))
- gmac->stats.rx_crc_errors++;
- if (RX_ERROR_FRAME(rx_status))
- gmac->stats.rx_frame_errors++;
-
- return NULL;
- }
-
- skb = napi_get_frags(&gmac->napi);
- if (!skb)
- return NULL;
-
- if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
- skb->ip_summed = CHECKSUM_UNNECESSARY;
-
- gmac->stats.rx_bytes += frame_len;
- gmac->stats.rx_packets++;
- return skb;
-}
-
-static unsigned gmac_rx(struct net_device *dev, unsigned budget)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- void __iomem *ptr_reg = gmac->rxq_rwptr;
-
- static struct sk_buff *skb;
-
- DMA_RWPTR_T rw;
- unsigned short r, w;
- unsigned short m = (1 << gmac->rxq_order) -1;
- GMAC_RXDESC_T *rx = NULL;
- struct page* page = NULL;
- unsigned page_offs;
- unsigned int frame_len, frag_len;
- int frag_nr = 0;
-
- GMAC_RXDESC_0_T word0;
- GMAC_RXDESC_1_T word1;
- dma_addr_t mapping;
- GMAC_RXDESC_3_T word3;
-
- rw.bits32 = readl(ptr_reg);
- /* Reset interrupt as all packages until here are taken into account */
- writel(DEFAULT_Q0_INT_BIT << dev->dev_id,
- toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
- r = rw.bits.rptr;
- w = rw.bits.wptr;
-
- while (budget && w != r) {
- rx = gmac->rxq_ring + r;
- word0 = rx->word0;
- word1 = rx->word1;
- mapping = rx->word2.buf_adr;
- word3 = rx->word3;
-
- r++;
- r &= m;
-
- frag_len = word0.bits.buffer_size;
- frame_len =word1.bits.byte_count;
- page_offs = mapping & ~PAGE_MASK;
-
- if (unlikely(!mapping)) {
- netdev_err(dev, "rxq[%u]: HW BUG: zero DMA desc\n", r);
- goto err_drop;
- }
-
- page = pfn_to_page(dma_to_pfn(toe->dev, mapping));
-
- if (word3.bits32 & SOF_BIT) {
- if (unlikely(skb)) {
- napi_free_frags(&gmac->napi);
- gmac->stats.rx_dropped++;
- }
-
- skb = gmac_skb_if_good_frame(gmac, word0, frame_len);
- if (unlikely(!skb))
- goto err_drop;
-
- page_offs += NET_IP_ALIGN;
- frag_len -= NET_IP_ALIGN;
- frag_nr = 0;
-
- } else if (!skb) {
- put_page(page);
- continue;
- }
-
- if (word3.bits32 & EOF_BIT)
- frag_len = frame_len - skb->len;
-
- /* append page frag to skb */
- if (unlikely(frag_nr == MAX_SKB_FRAGS))
- goto err_drop;
-
- if (frag_len == 0)
- netdev_err(dev, "Received fragment with len = 0\n");
-
- skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
- skb->len += frag_len;
- skb->data_len += frag_len;
- skb->truesize += frag_len;
- frag_nr++;
-
- if (word3.bits32 & EOF_BIT) {
- napi_gro_frags(&gmac->napi);
- skb = NULL;
- --budget;
- }
- continue;
-
-err_drop:
- if (skb) {
- napi_free_frags(&gmac->napi);
- skb = NULL;
- }
-
- if (mapping)
- put_page(page);
-
- gmac->stats.rx_dropped++;
- }
-
- writew(r, ptr_reg);
- return budget;
-}
-
-static int gmac_napi_poll(struct napi_struct *napi, int budget)
-{
- struct gmac_private *gmac = netdev_priv(napi->dev);
- struct toe_private *toe = gmac->toe;
- unsigned rx;
- unsigned freeq_threshold = 1 << (toe->freeq_order - 1);
-
- u64_stats_update_begin(&gmac->rx_stats_syncp);
-
- rx = budget - gmac_rx(napi->dev, budget);
-
- if (rx == 0) {
- napi_gro_flush(napi, false);
- __napi_complete(napi);
- gmac_enable_rx_irq(napi->dev, 1);
- ++gmac->rx_napi_exits;
- }
-
- gmac->freeq_refill += rx;
- if (gmac->freeq_refill > freeq_threshold) {
- gmac->freeq_refill -= freeq_threshold;
- toe_fill_freeq(toe, 0);
- }
-
- u64_stats_update_end(&gmac->rx_stats_syncp);
- return budget;
-}
-
-static void gmac_dump_dma_state(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- void __iomem *ptr_reg;
- unsigned reg[5];
-
- /* Interrupt status */
- reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
- reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
- reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
- reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
- reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
- netdev_err(dev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- reg[0], reg[1], reg[2], reg[3], reg[4]);
-
- /* Interrupt enable */
- reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
- reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
- reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
- reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
- reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
- netdev_err(dev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- reg[0], reg[1], reg[2], reg[3], reg[4]);
-
- /* RX DMA status */
- reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_FIRST_DESC_REG);
- reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_CURR_DESC_REG);
- reg[2] = GET_RPTR(gmac->rxq_rwptr);
- reg[3] = GET_WPTR(gmac->rxq_rwptr);
- netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
- reg[0], reg[1], reg[2], reg[3]);
-
- reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD0_REG);
- reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD1_REG);
- reg[2] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD2_REG);
- reg[3] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD3_REG);
- netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
- reg[0], reg[1], reg[2], reg[3]);
-
- /* TX DMA status */
- ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG;
-
- reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_FIRST_DESC_REG);
- reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_CURR_DESC_REG);
- reg[2] = GET_RPTR(ptr_reg);
- reg[3] = GET_WPTR(ptr_reg);
- netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
- reg[0], reg[1], reg[2], reg[3]);
-
- reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD0_REG);
- reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD1_REG);
- reg[2] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD2_REG);
- reg[3] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD3_REG);
- netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
- reg[0], reg[1], reg[2], reg[3]);
-
- /* FREE queues status */
- ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG;
-
- reg[0] = GET_RPTR(ptr_reg);
- reg[1] = GET_WPTR(ptr_reg);
-
- ptr_reg = toe->iomem + GLOBAL_HWFQ_RWPTR_REG;
-
- reg[2] = GET_RPTR(ptr_reg);
- reg[3] = GET_WPTR(ptr_reg);
- netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
- reg[0], reg[1], reg[2], reg[3]);
-}
-
-static void gmac_update_hw_stats(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned long flags;
- unsigned int rx_discards, rx_mcast, rx_bcast;
-
- spin_lock_irqsave(&toe->irq_lock, flags);
- u64_stats_update_begin(&gmac->ir_stats_syncp);
-
- gmac->hw_stats[0] += rx_discards = readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
- gmac->hw_stats[1] += readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
- gmac->hw_stats[2] += rx_mcast = readl(gmac->ctl_iomem + GMAC_IN_MCAST);
- gmac->hw_stats[3] += rx_bcast = readl(gmac->ctl_iomem + GMAC_IN_BCAST);
- gmac->hw_stats[4] += readl(gmac->ctl_iomem + GMAC_IN_MAC1);
- gmac->hw_stats[5] += readl(gmac->ctl_iomem + GMAC_IN_MAC2);
-
- gmac->stats.rx_missed_errors += rx_discards;
- gmac->stats.multicast += rx_mcast;
- gmac->stats.multicast += rx_bcast;
-
- writel(GMAC0_MIB_INT_BIT << (dev->dev_id * 8),
- toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
-
- u64_stats_update_end(&gmac->ir_stats_syncp);
- spin_unlock_irqrestore(&toe->irq_lock, flags);
-}
-
-static inline unsigned gmac_get_intr_flags(struct net_device *dev, int i)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- void __iomem *irqif_reg, *irqen_reg;
- unsigned offs, val;
-
- offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - GLOBAL_INTERRUPT_STATUS_0_REG);
-
- irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
- irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
-
- val = readl(irqif_reg) & readl(irqen_reg);
- return val;
-}
-
-enum hrtimer_restart gmac_coalesce_delay_expired( struct hrtimer *timer )
-{
- struct gmac_private *gmac = container_of(timer, struct gmac_private, rx_coalesce_timer);
-
- napi_schedule(&gmac->napi);
- return HRTIMER_NORESTART;
-}
-
-static irqreturn_t gmac_irq(int irq, void *data)
-{
- struct net_device *dev = data;
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- unsigned val, orr = 0;
-
- orr |= val = gmac_get_intr_flags(dev, 0);
-
- if (unlikely(val & (GMAC0_IRQ0_2 << (dev->dev_id * 2)))) {
- /* oh, crap. */
- netdev_err(dev, "hw failure/sw bug\n");
- gmac_dump_dma_state(dev);
-
- /* don't know how to recover, just reduce losses */
- gmac_enable_irq(dev, 0);
- return IRQ_HANDLED;
- }
-
- if (val & (GMAC0_IRQ0_TXQ0_INTS << (dev->dev_id * 6)))
- gmac_tx_irq(dev, 0);
-
- orr |= val = gmac_get_intr_flags(dev, 1);
-
- if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id)) {
-
- gmac_enable_rx_irq(dev, 0);
-
- if (!gmac->rx_coalesce_nsecs)
- napi_schedule(&gmac->napi);
- else {
- ktime_t ktime;
- ktime = ktime_set(0, gmac->rx_coalesce_nsecs);
- hrtimer_start(&gmac->rx_coalesce_timer, ktime, HRTIMER_MODE_REL);
- }
- }
-
- orr |= val = gmac_get_intr_flags(dev, 4);
-
- if (unlikely(val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8))))
- gmac_update_hw_stats(dev);
-
- if (unlikely(val & (GMAC0_RX_OVERRUN_INT_BIT << (dev->dev_id * 8)))) {
- writel(GMAC0_RXDERR_INT_BIT << (dev->dev_id * 8),
- toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
-
- spin_lock(&toe->irq_lock);
- u64_stats_update_begin(&gmac->ir_stats_syncp);
- ++gmac->stats.rx_fifo_errors;
- u64_stats_update_end(&gmac->ir_stats_syncp);
- spin_unlock(&toe->irq_lock);
- }
-
- return orr ? IRQ_HANDLED : IRQ_NONE;
-}
-
-static void gmac_start_dma(struct gmac_private *gmac)
-{
- void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
- GMAC_DMA_CTRL_T dma_ctrl;
-
- dma_ctrl.bits32 = readl(dma_ctrl_reg);
- dma_ctrl.bits.rd_enable = 1;
- dma_ctrl.bits.td_enable = 1;
- dma_ctrl.bits.loopback = 0;
- dma_ctrl.bits.drop_small_ack = 0;
- dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
- dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
- dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
- dma_ctrl.bits.rd_bus = HSIZE_8;
- dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
- dma_ctrl.bits.td_burst_size = HBURST_INCR8;
- dma_ctrl.bits.td_bus = HSIZE_8;
-
- writel(dma_ctrl.bits32, dma_ctrl_reg);
-}
-
-static void gmac_stop_dma(struct gmac_private *gmac)
-{
- void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG;
- GMAC_DMA_CTRL_T dma_ctrl;
-
- dma_ctrl.bits32 = readl(dma_ctrl_reg);
- dma_ctrl.bits.rd_enable = 0;
- dma_ctrl.bits.td_enable = 0;
- writel(dma_ctrl.bits32, dma_ctrl_reg);
-}
-
-static int gmac_open(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- int err;
-
- if (!dev->phydev) {
- err = gmac_setup_phy(dev);
- if (err) {
- netif_err(gmac, ifup, dev,
- "PHY init failed: %d\n", err);
- return err;
- }
- }
-
- err = request_irq(dev->irq, gmac_irq,
- IRQF_SHARED, dev->name, dev);
- if (unlikely(err))
- return err;
-
- netif_carrier_off(dev);
- phy_start(dev->phydev);
-
- err = toe_resize_freeq(gmac->toe, dev->dev_id);
- if (unlikely(err))
- goto err_stop_phy;
-
- err = gmac_setup_rxq(dev);
- if (unlikely(err))
- goto err_stop_phy;
-
- err = gmac_setup_txqs(dev);
- if (unlikely(err)) {
- gmac_cleanup_rxq(dev);
- goto err_stop_phy;
- }
-
- napi_enable(&gmac->napi);
-
- gmac_start_dma(gmac);
- gmac_enable_irq(dev, 1);
- gmac_enable_tx_rx(dev);
- netif_tx_start_all_queues(dev);
-
- hrtimer_init(&gmac->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- gmac->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
- return 0;
-
-err_stop_phy:
- phy_stop(dev->phydev);
- free_irq(dev->irq, dev);
- return err;
-}
-
-static int gmac_stop(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
-
- hrtimer_cancel(&gmac->rx_coalesce_timer);
- netif_tx_stop_all_queues(dev);
- gmac_disable_tx_rx(dev);
- gmac_stop_dma(gmac);
- napi_disable(&gmac->napi);
-
- gmac_enable_irq(dev, 0);
- gmac_cleanup_rxq(dev);
- gmac_cleanup_txqs(dev);
-
- phy_stop(dev->phydev);
- free_irq(dev->irq, dev);
-
- gmac_update_hw_stats(dev);
- return 0;
-}
-
-static void gmac_set_rx_mode(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct netdev_hw_addr *ha;
- __u32 mc_filter[2];
- unsigned bit_nr;
- GMAC_RX_FLTR_T filter = { .bits = {
- .broadcast = 1,
- .multicast = 1,
- .unicast = 1,
- } };
-
- mc_filter[1] = mc_filter[0] = 0;
-
- if (dev->flags & IFF_PROMISC) {
- filter.bits.error = 1;
- filter.bits.promiscuous = 1;
- } else if (!(dev->flags & IFF_ALLMULTI)) {
- mc_filter[1] = mc_filter[0] = 0;
- netdev_for_each_mc_addr(ha, dev) {
- bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
- mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
- }
- }
-
- writel(mc_filter[0], gmac->ctl_iomem + GMAC_MCAST_FIL0);
- writel(mc_filter[1], gmac->ctl_iomem + GMAC_MCAST_FIL1);
- writel(filter.bits32, gmac->ctl_iomem + GMAC_RX_FLTR);
-}
-
-static void __gmac_set_mac_address(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- __le32 addr[3];
-
- memset(addr, 0, sizeof(addr));
- memcpy(addr, dev->dev_addr, ETH_ALEN);
-
- writel(le32_to_cpu(addr[0]), gmac->ctl_iomem + GMAC_STA_ADD0);
- writel(le32_to_cpu(addr[1]), gmac->ctl_iomem + GMAC_STA_ADD1);
- writel(le32_to_cpu(addr[2]), gmac->ctl_iomem + GMAC_STA_ADD2);
-}
-
-static int gmac_set_mac_address(struct net_device *dev, void *addr)
-{
- struct sockaddr *sa = addr;
-
- memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
- __gmac_set_mac_address(dev);
-
- return 0;
-}
-
-static void gmac_clear_hw_stats(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
-
- readl(gmac->ctl_iomem + GMAC_IN_DISCARDS);
- readl(gmac->ctl_iomem + GMAC_IN_ERRORS);
- readl(gmac->ctl_iomem + GMAC_IN_MCAST);
- readl(gmac->ctl_iomem + GMAC_IN_BCAST);
- readl(gmac->ctl_iomem + GMAC_IN_MAC1);
- readl(gmac->ctl_iomem + GMAC_IN_MAC2);
-}
-
-static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev,
- struct rtnl_link_stats64 *storage)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- unsigned int start;
-
- gmac_update_hw_stats(dev);
-
- /* racing with RX NAPI */
- do {
- start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
-
- storage->rx_packets = gmac->stats.rx_packets;
- storage->rx_bytes = gmac->stats.rx_bytes;
- storage->rx_errors = gmac->stats.rx_errors;
- storage->rx_dropped = gmac->stats.rx_dropped;
-
- storage->rx_length_errors = gmac->stats.rx_length_errors;
- storage->rx_over_errors = gmac->stats.rx_over_errors;
- storage->rx_crc_errors = gmac->stats.rx_crc_errors;
- storage->rx_frame_errors = gmac->stats.rx_frame_errors;
-
- } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
-
- /* racing with MIB and TX completion interrupts */
- do {
- start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
-
- storage->tx_errors = gmac->stats.tx_errors;
- storage->tx_packets = gmac->stats.tx_packets;
- storage->tx_bytes = gmac->stats.tx_bytes;
-
- storage->multicast = gmac->stats.multicast;
- storage->rx_missed_errors = gmac->stats.rx_missed_errors;
- storage->rx_fifo_errors = gmac->stats.rx_fifo_errors;
-
- } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
-
- /* racing with hard_start_xmit */
- do {
- start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
-
- storage->tx_dropped = gmac->stats.tx_dropped;
-
- } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
-
- storage->rx_dropped += storage->rx_missed_errors;
-
- return storage;
-}
-
-static int gmac_change_mtu(struct net_device *dev, int new_mtu)
-{
- int max_len = gmac_pick_rx_max_len(new_mtu);
-
- if (max_len < 0)
- return -EINVAL;
-
- gmac_disable_tx_rx(dev);
-
- dev->mtu = new_mtu;
- gmac_update_config0_reg(dev,
- max_len << CONFIG0_MAXLEN_SHIFT,
- CONFIG0_MAXLEN_MASK);
-
- netdev_update_features(dev);
-
- gmac_enable_tx_rx(dev);
-
- return 0;
-}
-
-static netdev_features_t gmac_fix_features(struct net_device *dev, netdev_features_t features)
-{
- if (dev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
- features &= ~GMAC_OFFLOAD_FEATURES;
-
- return features;
-}
-
-static int gmac_set_features(struct net_device *dev, netdev_features_t features)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- int enable = features & NETIF_F_RXCSUM;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&gmac->config_lock, flags);
-
- reg = readl(gmac->ctl_iomem + GMAC_CONFIG0);
- reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
- writel(reg, gmac->ctl_iomem + GMAC_CONFIG0);
-
- spin_unlock_irqrestore(&gmac->config_lock, flags);
- return 0;
-}
-
-static int gmac_get_sset_count(struct net_device *dev, int sset)
-{
- return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
-}
-
-static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
-{
- if (stringset != ETH_SS_STATS)
- return;
-
- memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
-}
-
-static void gmac_get_ethtool_stats(struct net_device *dev,
- struct ethtool_stats *estats, u64 *values)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- unsigned int start;
- u64 *p;
- int i;
-
- gmac_update_hw_stats(dev);
-
- /* racing with MIB interrupt */
- do {
- p = values;
- start = u64_stats_fetch_begin(&gmac->ir_stats_syncp);
-
- for (i = 0; i < RX_STATS_NUM; ++i)
- *p++ = gmac->hw_stats[i];
-
- } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start));
- values = p;
-
- /* racing with RX NAPI */
- do {
- p = values;
- start = u64_stats_fetch_begin(&gmac->rx_stats_syncp);
-
- for (i = 0; i < RX_STATUS_NUM; ++i)
- *p++ = gmac->rx_stats[i];
- for (i = 0; i < RX_CHKSUM_NUM; ++i)
- *p++ = gmac->rx_csum_stats[i];
- *p++ = gmac->rx_napi_exits;
-
- } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start));
- values = p;
-
- /* racing with TX start_xmit */
- do {
- p = values;
- start = u64_stats_fetch_begin(&gmac->tx_stats_syncp);
-
- for (i = 0; i < TX_MAX_FRAGS; ++i) {
- *values++ = gmac->tx_frag_stats[i];
- gmac->tx_frag_stats[i] = 0;
- }
- *values++ = gmac->tx_frags_linearized;
- *values++ = gmac->tx_hw_csummed;
-
- } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start));
-}
-
-static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
- if (!dev->phydev)
- return -ENXIO;
- return phy_ethtool_gset(dev->phydev, cmd);
-}
-
-static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
- if (!dev->phydev)
- return -ENXIO;
- return phy_ethtool_sset(dev->phydev, cmd);
-}
-
-static int gmac_nway_reset(struct net_device *dev)
-{
- if (!dev->phydev)
- return -ENXIO;
- return phy_start_aneg(dev->phydev);
-}
-
-static void gmac_get_pauseparam(struct net_device *dev,
- struct ethtool_pauseparam *pparam)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- GMAC_CONFIG0_T config0;
-
- config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
-
- pparam->rx_pause = config0.bits.rx_fc_en;
- pparam->tx_pause = config0.bits.tx_fc_en;
- pparam->autoneg = true;
-}
-
-static void gmac_get_ringparam(struct net_device *dev,
- struct ethtool_ringparam *rp)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- GMAC_CONFIG0_T config0;
-
- config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0);
-
- rp->rx_max_pending = 1 << 15;
- rp->rx_mini_max_pending = 0;
- rp->rx_jumbo_max_pending = 0;
- rp->tx_max_pending = 1 << 15;
-
- rp->rx_pending = 1 << gmac->rxq_order;
- rp->rx_mini_pending = 0;
- rp->rx_jumbo_pending = 0;
- rp->tx_pending = 1 << gmac->txq_order;
-}
-
-static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id);
-
-static int gmac_set_ringparam(struct net_device *dev,
- struct ethtool_ringparam *rp)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- struct toe_private *toe = gmac->toe;
- int err = 0;
-
- if (netif_running(dev))
- return -EBUSY;
-
- if (rp->rx_pending) {
- gmac->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
- err = toe_resize_freeq(toe, dev->dev_id);
- }
-
- if (rp->tx_pending)
- {
- gmac->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
- gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2);
- }
-
- return err;
-}
-
-static int gmac_get_coalesce(struct net_device *dev,
- struct ethtool_coalesce *ecmd)
-{
- struct gmac_private *gmac = netdev_priv(dev);
-
- ecmd->rx_max_coalesced_frames = 1;
- ecmd->tx_max_coalesced_frames = gmac->irq_every_tx_packets;
- ecmd->rx_coalesce_usecs = gmac->rx_coalesce_nsecs/1000;
-
- return 0;
-}
-
-static int gmac_set_coalesce(struct net_device *dev,
- struct ethtool_coalesce *ecmd)
-{
- struct gmac_private *gmac = netdev_priv(dev);
-
- if (ecmd->tx_max_coalesced_frames < 1)
- return -EINVAL;
- if (ecmd->tx_max_coalesced_frames >= 1 << gmac->txq_order)
- return -EINVAL;
-
- gmac->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
- gmac->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
-
- return 0;
-}
-
-static u32 gmac_get_msglevel(struct net_device *dev)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- return gmac->msg_enable;
-}
-
-static void gmac_set_msglevel(struct net_device *dev, u32 level)
-{
- struct gmac_private *gmac = netdev_priv(dev);
- gmac->msg_enable = level;
-}
-
-static void gmac_get_drvinfo(struct net_device *dev,
- struct ethtool_drvinfo *info)
-{
- strcpy(info->driver, DRV_NAME);
- strcpy(info->version, DRV_VERSION);
- strcpy(info->bus_info, dev->dev_id ? "1" : "0");
-}
-
-static const struct net_device_ops gmac_351x_ops = {
- .ndo_init = gmac_init,
- .ndo_uninit = gmac_uninit,
- .ndo_open = gmac_open,
- .ndo_stop = gmac_stop,
- .ndo_start_xmit = gmac_start_xmit,
- .ndo_tx_timeout = gmac_tx_timeout,
- .ndo_set_rx_mode = gmac_set_rx_mode,
- .ndo_set_mac_address = gmac_set_mac_address,
- .ndo_get_stats64 = gmac_get_stats64,
- .ndo_change_mtu = gmac_change_mtu,
- .ndo_fix_features = gmac_fix_features,
- .ndo_set_features = gmac_set_features,
-};
-
-static const struct ethtool_ops gmac_351x_ethtool_ops = {
- .get_sset_count = gmac_get_sset_count,
- .get_strings = gmac_get_strings,
- .get_ethtool_stats = gmac_get_ethtool_stats,
- .get_settings = gmac_get_settings,
- .set_settings = gmac_set_settings,
- .get_link = ethtool_op_get_link,
- .nway_reset = gmac_nway_reset,
- .get_pauseparam = gmac_get_pauseparam,
- .get_ringparam = gmac_get_ringparam,
- .set_ringparam = gmac_set_ringparam,
- .get_coalesce = gmac_get_coalesce,
- .set_coalesce = gmac_set_coalesce,
- .get_msglevel = gmac_get_msglevel,
- .set_msglevel = gmac_set_msglevel,
- .get_drvinfo = gmac_get_drvinfo,
-};
-
-static int gmac_init_netdev(struct toe_private *toe, int num,
- struct platform_device *pdev)
-{
- struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
- struct gmac_private *gmac;
- struct net_device *dev;
- int irq, err;
-
- if (!pdata->bus_id[num])
- return 0;
-
- irq = platform_get_irq(pdev, num);
- if (irq < 0) {
- dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num);
- return irq;
- }
-
- dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM);
- if (!dev) {
- dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num);
- return -ENOMEM;
- }
-
- gmac = netdev_priv(dev);
- gmac->num = num;
- gmac->toe = toe;
- SET_NETDEV_DEV(dev, toe->dev);
-
- toe->netdev[num] = dev;
- dev->dev_id = num;
-
- gmac->ctl_iomem = toe->iomem + TOE_GMAC_BASE(num);
- gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num);
- dev->irq = irq;
-
- dev->netdev_ops = &gmac_351x_ops;
- dev->ethtool_ops = &gmac_351x_ethtool_ops;
-
- spin_lock_init(&gmac->config_lock);
- gmac_clear_hw_stats(dev);
-
- dev->hw_features = GMAC_OFFLOAD_FEATURES;
- dev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
-
- gmac->freeq_refill = 0;
- netif_napi_add(dev, &gmac->napi, gmac_napi_poll, DEFAULT_NAPI_WEIGHT);
-
- if (is_valid_ether_addr((void *)toe->mac_addr[num]))
- memcpy(dev->dev_addr, toe->mac_addr[num], ETH_ALEN);
- else
- random_ether_addr(dev->dev_addr);
- __gmac_set_mac_address(dev);
-
- err = gmac_setup_phy(dev);
- if (err)
- netif_warn(gmac, probe, dev,
- "PHY init failed: %d, deferring to ifup time\n", err);
-
- err = register_netdev(dev);
- if (!err)
- {
- pr_info(DRV_NAME " %s: irq %d, dma base 0x%p, io base 0x%p\n",
- dev->name, irq, gmac->dma_iomem, gmac->ctl_iomem);
- return 0;
- }
-
- toe->netdev[num] = NULL;
- free_netdev(dev);
- return err;
-}
-
-static irqreturn_t toe_irq_thread(int irq, void *data)
-{
- struct toe_private *toe = data;
- void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
- void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
- unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
- unsigned long flags;
-
- toe_fill_freeq(toe, 0);
-
- /* Ack and enable interrupt */
- spin_lock_irqsave(&toe->irq_lock, flags);
- writel(irqmask, irqif_reg);
- irqmask |= readl(irqen_reg);
- writel(irqmask, irqen_reg);
- spin_unlock_irqrestore(&toe->irq_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t toe_irq(int irq, void *data)
-{
- struct toe_private *toe = data;
- void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG;
- void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG;
- unsigned long val, en;
- irqreturn_t ret = IRQ_NONE;
-
- spin_lock(&toe->irq_lock);
-
- val = readl(irqif_reg);
- en = readl(irqen_reg);
-
- if (val & en & SWFQ_EMPTY_INT_BIT) {
- en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
- | GMAC1_RX_OVERRUN_INT_BIT);
- writel(en, irqen_reg);
- ret = IRQ_WAKE_THREAD;
- }
-
- spin_unlock(&toe->irq_lock);
- return ret;
-}
-
-static int toe_init(struct toe_private *toe,
- struct platform_device *pdev)
-{
- int err;
-
- writel(0, toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
- writel(0, toe->iomem + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
- writel(0, toe->iomem + GLOBAL_SWFQ_RWPTR_REG);
- writel(0, toe->iomem + GLOBAL_HWFQ_RWPTR_REG);
-
- toe->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
- toe->freeq_order = ~0;
-
- err = request_threaded_irq(toe->irq, toe_irq,
- toe_irq_thread, IRQF_SHARED, DRV_NAME " toe", toe);
- if (err)
- goto err_freeq;
-
- return 0;
-
-err_freeq:
- toe_cleanup_freeq(toe);
- return err;
-}
-
-static void toe_deinit(struct toe_private *toe)
-{
- free_irq(toe->irq, toe);
- toe_cleanup_freeq(toe);
-}
-
-static int toe_reset(struct toe_private *toe)
-{
- unsigned int reg = 0, retry = 5;
-
- reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
- GLOBAL_RESET));
- reg |= RESET_GMAC1 | RESET_GMAC0;
- writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
- GLOBAL_RESET));
-
- do {
- udelay(2);
- reg = readl((void __iomem*)(toe->iomem +
- GLOBAL_TOE_VERSION_REG));
- barrier();
- } while (!reg && --retry);
-
- return reg ? 0 : -EIO;
-}
-
-/*
- * Interrupt config:
- *
- * GMAC0 intr bits ------> int0 ----> eth0
- * GMAC1 intr bits ------> int1 ----> eth1
- * TOE intr -------------> int1 ----> eth1
- * Classification Intr --> int0 ----> eth0
- * Default Q0 -----------> int0 ----> eth0
- * Default Q1 -----------> int1 ----> eth1
- * FreeQ intr -----------> int1 ----> eth1
- */
-static void toe_init_irq(struct toe_private *toe)
-{
- writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG);
- writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG);
- writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG);
- writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG);
- writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG);
-
- writel(0xCCFC0FC0, toe->iomem + GLOBAL_INTERRUPT_SELECT_0_REG);
- writel(0x00F00002, toe->iomem + GLOBAL_INTERRUPT_SELECT_1_REG);
- writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_2_REG);
- writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_3_REG);
- writel(0xFF000003, toe->iomem + GLOBAL_INTERRUPT_SELECT_4_REG);
-
- /* edge-triggered interrupts packed to level-triggered one... */
- writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG);
- writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG);
- writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG);
- writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG);
- writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG);
-}
-
-static void toe_save_mac_addr(struct toe_private *toe,
- struct platform_device *pdev)
-{
- struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
- void __iomem *ctl;
- int i;
-
- for (i = 0; i < 2; i++) {
- if (pdata->bus_id[i]) {
- ctl = toe->iomem + TOE_GMAC_BASE(i);
- toe->mac_addr[i][0] = cpu_to_le32(readl(ctl + GMAC_STA_ADD0));
- toe->mac_addr[i][1] = cpu_to_le32(readl(ctl + GMAC_STA_ADD1));
- toe->mac_addr[i][2] = cpu_to_le32(readl(ctl + GMAC_STA_ADD2));
- }
- }
-}
-
-static int gemini_gmac_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct toe_private *toe;
- int irq, retval;
-
- if (!pdev->dev.platform_data)
- return -EINVAL;
-
- irq = platform_get_irq(pdev, 1);
- if (irq < 0)
- return irq;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev, "can't get device resources\n");
- return -ENODEV;
- }
-
- toe = kzalloc(sizeof(*toe), GFP_KERNEL);
- if (!toe)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, toe);
- toe->dev = &pdev->dev;
- toe->irq = irq;
-
- toe->iomem = ioremap(res->start, resource_size(res));
- if (!toe->iomem) {
- dev_err(toe->dev, "ioremap failed\n");
- retval = -EIO;
- goto err_data;
- }
-
- toe_save_mac_addr(toe, pdev);
-
- retval = toe_reset(toe);
- if (retval < 0)
- goto err_unmap;
-
- pr_info(DRV_NAME " toe: irq %d, io base 0x%08x, version %d\n",
- irq, res->start, retval);
-
- spin_lock_init(&toe->irq_lock);
- spin_lock_init(&toe->freeq_lock);
-
- toe_init_irq(toe);
-
- retval = toe_init(toe, pdev);
- if (retval)
- goto err_unmap;
-
- retval = gmac_init_netdev(toe, 0, pdev);
- if (retval)
- goto err_uninit;
-
- retval = gmac_init_netdev(toe, 1, pdev);
- if (retval)
- goto err_uninit;
-
- return 0;
-
-err_uninit:
- if (toe->netdev[0])
- unregister_netdev(toe->netdev[0]);
- toe_deinit(toe);
-err_unmap:
- iounmap(toe->iomem);
-err_data:
- kfree(toe);
- return retval;
-}
-
-static int gemini_gmac_remove(struct platform_device *pdev)
-{
- struct toe_private *toe = platform_get_drvdata(pdev);
- int i;
-
- for (i = 0; i < 2; i++)
- if (toe->netdev[i])
- unregister_netdev(toe->netdev[i]);
-
- toe_init_irq(toe);
- toe_deinit(toe);
-
- iounmap(toe->iomem);
- kfree(toe);
-
- return 0;
-}
-
-static struct platform_driver gemini_gmac_driver = {
- .probe = gemini_gmac_probe,
- .remove = gemini_gmac_remove,
- .driver.name = DRV_NAME,
- .driver.owner = THIS_MODULE,
-};
-
-static int __init gemini_gmac_init(void)
-{
-#ifdef CONFIG_MDIO_GPIO_MODULE
- request_module("mdio-gpio");
-#endif
- return platform_driver_register(&gemini_gmac_driver);
-}
-
-static void __exit gemini_gmac_exit(void)
-{
- platform_driver_unregister(&gemini_gmac_driver);
-}
-
-module_init(gemini_gmac_init);
-module_exit(gemini_gmac_exit);
diff --git a/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x_hw.h b/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x_hw.h
deleted file mode 100644
index f7bff5ace2fe..000000000000
--- a/target/linux/gemini/files/drivers/net/ethernet/gemini/sl351x_hw.h
+++ /dev/null
@@ -1,1436 +0,0 @@
-/*
- * Register definitions for Gemini LEPUS GMAC Ethernet device driver.
- *
- * Copyright (C) 2006, Storlink, Corp.
- * Copyright (C) 2008-2009, Paulius Zaleckas <***@teltonika.lt>
- * Copyright (C) 2010, Michał Mirosław <mirq-***@rere.qmqm.pl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef _GMAC_HW_H
-#define _GMAC_HW_H
-
-#include <linux/bitops.h>
-
-/*
- * Base Registers
- */
-#define TOE_NONTOE_QUE_HDR_BASE 0x2000
-#define TOE_TOE_QUE_HDR_BASE 0x3000
-#define TOE_V_BIT_BASE 0x4000
-#define TOE_A_BIT_BASE 0x6000
-#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
-#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
-
-/*
- * Queue ID
- */
-#define TOE_SW_FREE_QID 0x00
-#define TOE_HW_FREE_QID 0x01
-#define TOE_GMAC0_SW_TXQ0_QID 0x02
-#define TOE_GMAC0_SW_TXQ1_QID 0x03
-#define TOE_GMAC0_SW_TXQ2_QID 0x04
-#define TOE_GMAC0_SW_TXQ3_QID 0x05
-#define TOE_GMAC0_SW_TXQ4_QID 0x06
-#define TOE_GMAC0_SW_TXQ5_QID 0x07
-#define TOE_GMAC0_HW_TXQ0_QID 0x08
-#define TOE_GMAC0_HW_TXQ1_QID 0x09
-#define TOE_GMAC0_HW_TXQ2_QID 0x0A
-#define TOE_GMAC0_HW_TXQ3_QID 0x0B
-#define TOE_GMAC1_SW_TXQ0_QID 0x12
-#define TOE_GMAC1_SW_TXQ1_QID 0x13
-#define TOE_GMAC1_SW_TXQ2_QID 0x14
-#define TOE_GMAC1_SW_TXQ3_QID 0x15
-#define TOE_GMAC1_SW_TXQ4_QID 0x16
-#define TOE_GMAC1_SW_TXQ5_QID 0x17
-#define TOE_GMAC1_HW_TXQ0_QID 0x18
-#define TOE_GMAC1_HW_TXQ1_QID 0x19
-#define TOE_GMAC1_HW_TXQ2_QID 0x1A
-#define TOE_GMAC1_HW_TXQ3_QID 0x1B
-#define TOE_GMAC0_DEFAULT_QID 0x20
-#define TOE_GMAC1_DEFAULT_QID 0x21
-#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
-#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
-
-/*
- * old info:
- * TOE DMA Queue Size should be 2^n, n = 6...12
- * TOE DMA Queues are the following queue types:
- * SW Free Queue, HW Free Queue,
- * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
- * The base address and descriptor number are configured at
- * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
- */
-
-#define GET_WPTR(addr) __raw_readw((addr) + 2)
-#define GET_RPTR(addr) __raw_readw((addr))
-#define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2)
-#define SET_RPTR(addr, data) __raw_writew((data), (addr))
-#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
-#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
-#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
-#define __RWPTR_MASK(order) ((1 << (order)) - 1)
-#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
-#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
-#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
- __RWPTR_MASK((order)))
-
-/*
- * Global registers
- * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
- * Base 0x60000000
- */
-#define GLOBAL_TOE_VERSION_REG 0x0000
-#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
-#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
-#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
-#define GLOBAL_SWFQ_RWPTR_REG 0x0014
-#define GLOBAL_HWFQ_RWPTR_REG 0x0018
-#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
-#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
-#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
-#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
-#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
-#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
-#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
-#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
-#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
-#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
-#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
-#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
-#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
-#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
-#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
-#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
-#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
-
-/*
- * GMAC 0/1 DMA/TOE register
- * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
- * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
- * Base 0x60008000 or 0x6000C000
- */
-#define GMAC_DMA_CTRL_REG 0x0000
-#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
-#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
-#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
-#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
-#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
-#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
-#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
-#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
-#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
-#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
-#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
-#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
-#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
-#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
-#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
-#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
-#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
-#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
-#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
-#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
-#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
-#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
-#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
-#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
-#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
-#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
-#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
-#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
-#define GMAC_HASH_ENGINE_REG0 0x0070
-#define GMAC_HASH_ENGINE_REG1 0x0074
-/* matching rule 0 Control register 0 */
-#define GMAC_MR0CR0 0x0078
-#define GMAC_MR0CR1 0x007C
-#define GMAC_MR0CR2 0x0080
-#define GMAC_MR1CR0 0x0084
-#define GMAC_MR1CR1 0x0088
-#define GMAC_MR1CR2 0x008C
-#define GMAC_MR2CR0 0x0090
-#define GMAC_MR2CR1 0x0094
-#define GMAC_MR2CR2 0x0098
-#define GMAC_MR3CR0 0x009C
-#define GMAC_MR3CR1 0x00A0
-#define GMAC_MR3CR2 0x00A4
-/* Support Protocol Regsister 0 */
-#define GMAC_SPR0 0x00A8
-#define GMAC_SPR1 0x00AC
-#define GMAC_SPR2 0x00B0
-#define GMAC_SPR3 0x00B4
-#define GMAC_SPR4 0x00B8
-#define GMAC_SPR5 0x00BC
-#define GMAC_SPR6 0x00C0
-#define GMAC_SPR7 0x00C4
-/* GMAC Hash/Rx/Tx AHB Weighting register */
-#define GMAC_AHB_WEIGHT_REG 0x00C8
-
-/*
- * TOE GMAC 0/1 register
- * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
- * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
- * Base 0x6000A000 or 0x6000E000
- */
-enum GMAC_REGISTER {
- GMAC_STA_ADD0 = 0x0000,
- GMAC_STA_ADD1 = 0x0004,
- GMAC_STA_ADD2 = 0x0008,
- GMAC_RX_FLTR = 0x000c,
- GMAC_MCAST_FIL0 = 0x0010,
- GMAC_MCAST_FIL1 = 0x0014,
- GMAC_CONFIG0 = 0x0018,
- GMAC_CONFIG1 = 0x001c,
- GMAC_CONFIG2 = 0x0020,
- GMAC_CONFIG3 = 0x0024,
- GMAC_RESERVED = 0x0028,
- GMAC_STATUS = 0x002c,
- GMAC_IN_DISCARDS= 0x0030,
- GMAC_IN_ERRORS = 0x0034,
- GMAC_IN_MCAST = 0x0038,
- GMAC_IN_BCAST = 0x003c,
- GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
- GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
-};
-
-#define RX_STATS_NUM 6
-
-/*
- * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
- */
-typedef union {
- unsigned int bits32;
- unsigned int base_size;
-} DMA_Q_BASE_SIZE_T;
-#define DMA_Q_BASE_MASK (~0x0f)
-
-/*
- * DMA SKB Buffer register (offset 0x0008)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0008 {
- unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
- unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
- } bits;
-} DMA_SKB_SIZE_T;
-
-/*
- * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
- */
-typedef union {
- unsigned int bits32;
- struct bit_000c {
- unsigned int rptr : 16; /* Read Ptr, RO */
- unsigned int wptr : 16; /* Write Ptr, RW */
- } bits;
-} DMA_RWPTR_T;
-
-/*
- * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
- * see DMA_RWPTR_T structure
- */
-
-/*
- * Interrupt Status Register 0 (offset 0x0020)
- * Interrupt Mask Register 0 (offset 0x0024)
- * Interrupt Select Register 0 (offset 0x0028)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0020 {
- /* GMAC0 SW Tx Queue 0 EOF Interrupt */
- unsigned int swtq00_eof : 1;
- unsigned int swtq01_eof : 1;
- unsigned int swtq02_eof : 1;
- unsigned int swtq03_eof : 1;
- unsigned int swtq04_eof : 1;
- unsigned int swtq05_eof : 1;
- /* GMAC1 SW Tx Queue 0 EOF Interrupt */
- unsigned int swtq10_eof : 1;
- unsigned int swtq11_eof : 1;
- unsigned int swtq12_eof : 1;
- unsigned int swtq13_eof : 1;
- unsigned int swtq14_eof : 1;
- unsigned int swtq15_eof : 1;
- /* GMAC0 SW Tx Queue 0 Finish Interrupt */
- unsigned int swtq00_fin : 1;
- unsigned int swtq01_fin : 1;
- unsigned int swtq02_fin : 1;
- unsigned int swtq03_fin : 1;
- unsigned int swtq04_fin : 1;
- unsigned int swtq05_fin : 1;
- /* GMAC1 SW Tx Queue 0 Finish Interrupt */
- unsigned int swtq10_fin : 1;
- unsigned int swtq11_fin : 1;
- unsigned int swtq12_fin : 1;
- unsigned int swtq13_fin : 1;
- unsigned int swtq14_fin : 1;
- unsigned int swtq15_fin : 1;
- /* GMAC0 Rx Descriptor Protocol Error */
- unsigned int rxPerr0 : 1;
- /* GMAC0 AHB Bus Error while Rx */
- unsigned int rxDerr0 : 1;
- /* GMAC1 Rx Descriptor Protocol Error */
- unsigned int rxPerr1 : 1;
- /* GMAC1 AHB Bus Error while Rx */
- unsigned int rxDerr1 : 1;
- /* GMAC0 Tx Descriptor Protocol Error */
- unsigned int txPerr0 : 1;
- /* GMAC0 AHB Bus Error while Tx */
- unsigned int txDerr0 : 1;
- /* GMAC1 Tx Descriptor Protocol Error */
- unsigned int txPerr1 : 1;
- /* GMAC1 AHB Bus Error while Tx */
- unsigned int txDerr1 : 1;
- } bits;
-} INTR_REG0_T;
-
-#define GMAC1_TXDERR_INT_BIT BIT(31)
-#define GMAC1_TXPERR_INT_BIT BIT(30)
-#define GMAC0_TXDERR_INT_BIT BIT(29)
-#define GMAC0_TXPERR_INT_BIT BIT(28)
-#define GMAC1_RXDERR_INT_BIT BIT(27)
-#define GMAC1_RXPERR_INT_BIT BIT(26)
-#define GMAC0_RXDERR_INT_BIT BIT(25)
-#define GMAC0_RXPERR_INT_BIT BIT(24)
-#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
-#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
-#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
-#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
-#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
-#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
-#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
-#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
-#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
-#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
-#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
-#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
-#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
-#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
-#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
-#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
-#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
-#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
-#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
-#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
-#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
-#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
-#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
-#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
-
-/*
- * Interrupt Status Register 1 (offset 0x0030)
- * Interrupt Mask Register 1 (offset 0x0034)
- * Interrupt Select Register 1 (offset 0x0038)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0030 {
- unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
- unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
- unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
- unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
- unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
- unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
- unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
- unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
- unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
- unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
- unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
- unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
- unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
- unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
- unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
- unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
- unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
- unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
- unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
- } bits;
-} INTR_REG1_T;
-
-#define TOE_IQ3_FULL_INT_BIT BIT(31)
-#define TOE_IQ2_FULL_INT_BIT BIT(30)
-#define TOE_IQ1_FULL_INT_BIT BIT(29)
-#define TOE_IQ0_FULL_INT_BIT BIT(28)
-#define TOE_IQ3_INT_BIT BIT(27)
-#define TOE_IQ2_INT_BIT BIT(26)
-#define TOE_IQ1_INT_BIT BIT(25)
-#define TOE_IQ0_INT_BIT BIT(24)
-#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
-#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
-#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
-#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
-#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
-#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
-#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
-#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
-#define CLASS_RX_INT_BIT(x) BIT((x + 2))
-#define DEFAULT_Q1_INT_BIT BIT(1)
-#define DEFAULT_Q0_INT_BIT BIT(0)
-
-#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
- TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
-#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
- TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
-#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
-#define TOE_CLASS_RX_INT_BITS 0xfffc
-
-/*
- * Interrupt Status Register 2 (offset 0x0040)
- * Interrupt Mask Register 2 (offset 0x0044)
- * Interrupt Select Register 2 (offset 0x0048)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0040 {
- unsigned int toe_q0_full : 1; /* bit 0 TOE Queue 0 Full Interrupt */
- unsigned int toe_q1_full : 1; /* bit 1 TOE Queue 1 Full Interrupt */
- unsigned int toe_q2_full : 1; /* bit 2 TOE Queue 2 Full Interrupt */
- unsigned int toe_q3_full : 1; /* bit 3 TOE Queue 3 Full Interrupt */
- unsigned int toe_q4_full : 1; /* bit 4 TOE Queue 4 Full Interrupt */
- unsigned int toe_q5_full : 1; /* bit 5 TOE Queue 5 Full Interrupt */
- unsigned int toe_q6_full : 1; /* bit 6 TOE Queue 6 Full Interrupt */
- unsigned int toe_q7_full : 1; /* bit 7 TOE Queue 7 Full Interrupt */
- unsigned int toe_q8_full : 1; /* bit 8 TOE Queue 8 Full Interrupt */
- unsigned int toe_q9_full : 1; /* bit 9 TOE Queue 9 Full Interrupt */
- unsigned int toe_q10_full : 1; /* bit 10 TOE Queue 10 Full Interrupt */
- unsigned int toe_q11_full : 1; /* bit 11 TOE Queue 11 Full Interrupt */
- unsigned int toe_q12_full : 1; /* bit 12 TOE Queue 12 Full Interrupt */
- unsigned int toe_q13_full : 1; /* bit 13 TOE Queue 13 Full Interrupt */
- unsigned int toe_q14_full : 1; /* bit 14 TOE Queue 14 Full Interrupt */
- unsigned int toe_q15_full : 1; /* bit 15 TOE Queue 15 Full Interrupt */
- unsigned int toe_q16_full : 1; /* bit 16 TOE Queue 16 Full Interrupt */
- unsigned int toe_q17_full : 1; /* bit 17 TOE Queue 17 Full Interrupt */
- unsigned int toe_q18_full : 1; /* bit 18 TOE Queue 18 Full Interrupt */
- unsigned int toe_q19_full : 1; /* bit 19 TOE Queue 19 Full Interrupt */
- unsigned int toe_q20_full : 1; /* bit 20 TOE Queue 20 Full Interrupt */
- unsigned int toe_q21_full : 1; /* bit 21 TOE Queue 21 Full Interrupt */
- unsigned int toe_q22_full : 1; /* bit 22 TOE Queue 22 Full Interrupt */
- unsigned int toe_q23_full : 1; /* bit 23 TOE Queue 23 Full Interrupt */
- unsigned int toe_q24_full : 1; /* bit 24 TOE Queue 24 Full Interrupt */
- unsigned int toe_q25_full : 1; /* bit 25 TOE Queue 25 Full Interrupt */
- unsigned int toe_q26_full : 1; /* bit 26 TOE Queue 26 Full Interrupt */
- unsigned int toe_q27_full : 1; /* bit 27 TOE Queue 27 Full Interrupt */
- unsigned int toe_q28_full : 1; /* bit 28 TOE Queue 28 Full Interrupt */
- unsigned int toe_q29_full : 1; /* bit 29 TOE Queue 29 Full Interrupt */
- unsigned int toe_q30_full : 1; /* bit 30 TOE Queue 30 Full Interrupt */
- unsigned int toe_q31_full : 1; /* bit 31 TOE Queue 31 Full Interrupt */
- } bits;
-} INTR_REG2_T;
-
-#define TOE_QL_FULL_INT_BIT(x) BIT(x)
-
-/*
- * Interrupt Status Register 3 (offset 0x0050)
- * Interrupt Mask Register 3 (offset 0x0054)
- * Interrupt Select Register 3 (offset 0x0058)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0050 {
- unsigned int toe_q32_full : 1; /* bit 32 TOE Queue 32 Full Interrupt */
- unsigned int toe_q33_full : 1; /* bit 33 TOE Queue 33 Full Interrupt */
- unsigned int toe_q34_full : 1; /* bit 34 TOE Queue 34 Full Interrupt */
- unsigned int toe_q35_full : 1; /* bit 35 TOE Queue 35 Full Interrupt */
- unsigned int toe_q36_full : 1; /* bit 36 TOE Queue 36 Full Interrupt */
- unsigned int toe_q37_full : 1; /* bit 37 TOE Queue 37 Full Interrupt */
- unsigned int toe_q38_full : 1; /* bit 38 TOE Queue 38 Full Interrupt */
- unsigned int toe_q39_full : 1; /* bit 39 TOE Queue 39 Full Interrupt */
- unsigned int toe_q40_full : 1; /* bit 40 TOE Queue 40 Full Interrupt */
- unsigned int toe_q41_full : 1; /* bit 41 TOE Queue 41 Full Interrupt */
- unsigned int toe_q42_full : 1; /* bit 42 TOE Queue 42 Full Interrupt */
- unsigned int toe_q43_full : 1; /* bit 43 TOE Queue 43 Full Interrupt */
- unsigned int toe_q44_full : 1; /* bit 44 TOE Queue 44 Full Interrupt */
- unsigned int toe_q45_full : 1; /* bit 45 TOE Queue 45 Full Interrupt */
- unsigned int toe_q46_full : 1; /* bit 46 TOE Queue 46 Full Interrupt */
- unsigned int toe_q47_full : 1; /* bit 47 TOE Queue 47 Full Interrupt */
- unsigned int toe_q48_full : 1; /* bit 48 TOE Queue 48 Full Interrupt */
- unsigned int toe_q49_full : 1; /* bit 49 TOE Queue 49 Full Interrupt */
- unsigned int toe_q50_full : 1; /* bit 50 TOE Queue 50 Full Interrupt */
- unsigned int toe_q51_full : 1; /* bit 51 TOE Queue 51 Full Interrupt */
- unsigned int toe_q52_full : 1; /* bit 52 TOE Queue 52 Full Interrupt */
- unsigned int toe_q53_full : 1; /* bit 53 TOE Queue 53 Full Interrupt */
- unsigned int toe_q54_full : 1; /* bit 54 TOE Queue 54 Full Interrupt */
- unsigned int toe_q55_full : 1; /* bit 55 TOE Queue 55 Full Interrupt */
- unsigned int toe_q56_full : 1; /* bit 56 TOE Queue 56 Full Interrupt */
- unsigned int toe_q57_full : 1; /* bit 57 TOE Queue 57 Full Interrupt */
- unsigned int toe_q58_full : 1; /* bit 58 TOE Queue 58 Full Interrupt */
- unsigned int toe_q59_full : 1; /* bit 59 TOE Queue 59 Full Interrupt */
- unsigned int toe_q60_full : 1; /* bit 60 TOE Queue 60 Full Interrupt */
- unsigned int toe_q61_full : 1; /* bit 61 TOE Queue 61 Full Interrupt */
- unsigned int toe_q62_full : 1; /* bit 62 TOE Queue 62 Full Interrupt */
- unsigned int toe_q63_full : 1; /* bit 63 TOE Queue 63 Full Interrupt */
- } bits;
-} INTR_REG3_T;
-
-#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
-
-/*
- * Interrupt Status Register 4 (offset 0x0060)
- * Interrupt Mask Register 4 (offset 0x0064)
- * Interrupt Select Register 4 (offset 0x0068)
- */
-typedef union {
- unsigned char byte;
- struct bit_0060 {
- unsigned char status_changed : 1; /* Status Changed Intr for RGMII Mode */
- unsigned char rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */
- unsigned char tx_pause_off : 1; /* received pause off frame interrupt */
- unsigned char rx_pause_off : 1; /* received pause off frame interrupt */
- unsigned char tx_pause_on : 1; /* transmit pause on frame interrupt */
- unsigned char rx_pause_on : 1; /* received pause on frame interrupt */
- unsigned char cnt_full : 1; /* MIB counters half full interrupt */
- unsigned char reserved : 1; /* */
- } __packed bits;
-} __packed GMAC_INTR_T;
-
-typedef union {
- unsigned int bits32;
- struct bit_0060_2 {
- unsigned int swfq_empty : 1; /* bit 0 Software Free Queue Empty Intr. */
- unsigned int hwfq_empty : 1; /* bit 1 Hardware Free Queue Empty Intr. */
- unsigned int class_qf_int : 14; /* bit 15:2 Classification Rx Queue13-0 Full Intr. */
- GMAC_INTR_T gmac0;
- GMAC_INTR_T gmac1;
- } bits;
-} INTR_REG4_T;
-
-#define GMAC1_RESERVED_INT_BIT BIT(31)
-#define GMAC1_MIB_INT_BIT BIT(30)
-#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
-#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
-#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
-#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
-#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
-#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
-#define GMAC0_RESERVED_INT_BIT BIT(23)
-#define GMAC0_MIB_INT_BIT BIT(22)
-#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
-#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
-#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
-#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
-#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
-#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
-#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
-#define HWFQ_EMPTY_INT_BIT BIT(1)
-#define SWFQ_EMPTY_INT_BIT BIT(0)
-
-#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
- GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
- GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
- GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
-#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
- GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
- GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
- GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
-
-#define CLASS_RX_FULL_INT_BITS 0xfffc
-
-/*
- * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
- */
-typedef union {
- unsigned int bits32;
- struct bit_0070_2 {
- unsigned int swfq_empty : 8; /* 7:0 Software Free Queue Empty Threshold */
- unsigned int hwfq_empty : 8; /* 15:8 Hardware Free Queue Empty Threshold */
- unsigned int intrq : 8; /* 23:16 */
- unsigned int toe_class : 8; /* 31:24 */
- } bits;
-} QUEUE_THRESHOLD_T;
-
-
-/*
- * GMAC DMA Control Register
- * GMAC0 offset 0x8000
- * GMAC1 offset 0xC000
- */
-typedef union {
- unsigned int bits32;
- struct bit_8000 {
- unsigned int td_bus : 2; /* bit 1:0 Peripheral Bus Width */
- unsigned int td_burst_size : 2; /* bit 3:2 TxDMA max burst size for every AHB request */
- unsigned int td_prot : 4; /* bit 7:4 TxDMA protection control */
- unsigned int rd_bus : 2; /* bit 9:8 Peripheral Bus Width */
- unsigned int rd_burst_size : 2; /* bit 11:10 DMA max burst size for every AHB request */
- unsigned int rd_prot : 4; /* bit 15:12 DMA Protection Control */
- unsigned int rd_insert_bytes : 2; /* bit 17:16 */
- unsigned int reserved : 10; /* bit 27:18 */
- unsigned int drop_small_ack : 1; /* bit 28 1: Drop, 0: Accept */
- unsigned int loopback : 1; /* bit 29 Loopback TxDMA to RxDMA */
- unsigned int td_enable : 1; /* bit 30 Tx DMA Enable */
- unsigned int rd_enable : 1; /* bit 31 Rx DMA Enable */
- } bits;
-} GMAC_DMA_CTRL_T;
-
-/*
- * GMAC Tx Weighting Control Register 0
- * GMAC0 offset 0x8004
- * GMAC1 offset 0xC004
- */
-typedef union {
- unsigned int bits32;
- struct bit_8004 {
- unsigned int hw_tq0 : 6; /* bit 5:0 HW TX Queue 3 */
- unsigned int hw_tq1 : 6; /* bit 11:6 HW TX Queue 2 */
- unsigned int hw_tq2 : 6; /* bit 17:12 HW TX Queue 1 */
- unsigned int hw_tq3 : 6; /* bit 23:18 HW TX Queue 0 */
- unsigned int reserved : 8; /* bit 31:24 */
- } bits;
-} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
-
-/*
- * GMAC Tx Weighting Control Register 1
- * GMAC0 offset 0x8008
- * GMAC1 offset 0xC008
- */
-typedef union {
- unsigned int bits32;
- struct bit_8008 {
- unsigned int sw_tq0 : 5; /* bit 4:0 SW TX Queue 0 */
- unsigned int sw_tq1 : 5; /* bit 9:5 SW TX Queue 1 */
- unsigned int sw_tq2 : 5; /* bit 14:10 SW TX Queue 2 */
- unsigned int sw_tq3 : 5; /* bit 19:15 SW TX Queue 3 */
- unsigned int sw_tq4 : 5; /* bit 24:20 SW TX Queue 4 */
- unsigned int sw_tq5 : 5; /* bit 29:25 SW TX Queue 5 */
- unsigned int reserved : 2; /* bit 31:30 */
- } bits;
-} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
-
-/*
- * Queue Read/Write Pointer
- * GMAC SW TX Queue 0~5 Read/Write Pointer register
- * GMAC0 offset 0x800C ~ 0x8020
- * GMAC1 offset 0xC00C ~ 0xC020
- * GMAC HW TX Queue 0~3 Read/Write Pointer register
- * GMAC0 offset 0x8024 ~ 0x8030
- * GMAC1 offset 0xC024 ~ 0xC030
- *
- * see DMA_RWPTR_T structure
- */
-
-/*
- * GMAC DMA Tx First Description Address Register
- * GMAC0 offset 0x8038
- * GMAC1 offset 0xC038
- */
-typedef union {
- unsigned int bits32;
- struct bit_8038 {
- unsigned int reserved : 3;
- unsigned int td_busy : 1; /* bit 3 1: TxDMA busy; 0: TxDMA idle */
- unsigned int td_first_des_ptr : 28; /* bit 31:4 first descriptor address */
- } bits;
-} GMAC_TXDMA_FIRST_DESC_T;
-
-/*
- * GMAC DMA Tx Current Description Address Register
- * GMAC0 offset 0x803C
- * GMAC1 offset 0xC03C
- */
-typedef union {
- unsigned int bits32;
- struct bit_803C {
- unsigned int reserved : 4;
- unsigned int td_curr_desc_ptr : 28; /* bit 31:4 current descriptor address */
- } bits;
-} GMAC_TXDMA_CURR_DESC_T;
-
-/*
- * GMAC DMA Tx Description Word 0 Register
- * GMAC0 offset 0x8040
- * GMAC1 offset 0xC040
- */
-typedef union {
- unsigned int bits32;
- struct bit_8040 {
- unsigned int buffer_size : 16; /* bit 15:0 Transfer size */
- unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
- unsigned int status_tx_ok : 1; /* bit 22 Tx Status, 1: Successful 0: Failed */
- unsigned int status_rvd : 6; /* bit 28:23 Tx Status, Reserved bits */
- unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
- unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
- unsigned int reserved : 1; /* bit 31 */
- } bits;
-} GMAC_TXDESC_0_T;
-
-/*
- * GMAC DMA Tx Description Word 1 Register
- * GMAC0 offset 0x8044
- * GMAC1 offset 0xC044
- */
-typedef union {
- unsigned int bits32;
- struct txdesc_word1 {
- unsigned int byte_count : 16; /* bit 15: 0 Tx Frame Byte Count */
- unsigned int mtu_enable : 1; /* bit 16 TSS segmentation use MTU setting */
- unsigned int ip_chksum : 1; /* bit 17 IPV4 Header Checksum Enable */
- unsigned int ipv6_enable : 1; /* bit 18 IPV6 Tx Enable */
- unsigned int tcp_chksum : 1; /* bit 19 TCP Checksum Enable */
- unsigned int udp_chksum : 1; /* bit 20 UDP Checksum Enable */
- unsigned int bypass_tss : 1; /* bit 21 Bypass HW offload engine */
- unsigned int ip_fixed_len : 1; /* bit 22 Don't update IP length field */
- unsigned int reserved : 9; /* bit 31:23 Tx Flag, Reserved */
- } bits;
-} GMAC_TXDESC_1_T;
-
-#define TSS_IP_FIXED_LEN_BIT BIT(22)
-#define TSS_BYPASS_BIT BIT(21)
-#define TSS_UDP_CHKSUM_BIT BIT(20)
-#define TSS_TCP_CHKSUM_BIT BIT(19)
-#define TSS_IPV6_ENABLE_BIT BIT(18)
-#define TSS_IP_CHKSUM_BIT BIT(17)
-#define TSS_MTU_ENABLE_BIT BIT(16)
-
-#define TSS_CHECKUM_ENABLE \
- (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \
- TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT)
-
-/*
- * GMAC DMA Tx Description Word 2 Register
- * GMAC0 offset 0x8048
- * GMAC1 offset 0xC048
- */
-typedef union {
- unsigned int bits32;
- unsigned int buf_adr;
-} GMAC_TXDESC_2_T;
-
-/*
- * GMAC DMA Tx Description Word 3 Register
- * GMAC0 offset 0x804C
- * GMAC1 offset 0xC04C
- */
-typedef union {
- unsigned int bits32;
- struct txdesc_word3 {
- unsigned int mtu_size : 13; /* bit 12: 0 Tx Frame Byte Count */
- unsigned int reserved : 16; /* bit 28:13 */
- unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
- unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
- } bits;
-} GMAC_TXDESC_3_T;
-#define SOF_EOF_BIT_MASK 0x3fffffff
-#define SOF_BIT 0x80000000
-#define EOF_BIT 0x40000000
-#define EOFIE_BIT BIT(29)
-#define MTU_SIZE_BIT_MASK 0x1fff
-
-/*
- * GMAC Tx Descriptor
- */
-typedef struct {
- GMAC_TXDESC_0_T word0;
- GMAC_TXDESC_1_T word1;
- GMAC_TXDESC_2_T word2;
- GMAC_TXDESC_3_T word3;
-} GMAC_TXDESC_T;
-
-/*
- * GMAC DMA Rx First Description Address Register
- * GMAC0 offset 0x8058
- * GMAC1 offset 0xC058
- */
-typedef union {
- unsigned int bits32;
- struct bit_8058 {
- unsigned int reserved : 3; /* bit 2:0 */
- unsigned int rd_busy : 1; /* bit 3 1-RxDMA busy; 0-RxDMA idle */
- unsigned int rd_first_des_ptr : 28; /* bit 31:4 first descriptor address */
- } bits;
-} GMAC_RXDMA_FIRST_DESC_T;
-
-/*
- * GMAC DMA Rx Current Description Address Register
- * GMAC0 offset 0x805C
- * GMAC1 offset 0xC05C
- */
-typedef union {
- unsigned int bits32;
- struct bit_805C {
- unsigned int reserved : 4; /* bit 3:0 */
- unsigned int rd_curr_des_ptr : 28; /* bit 31:4 current descriptor address */
- } bits;
-} GMAC_RXDMA_CURR_DESC_T;
-
-/*
- * GMAC DMA Rx Description Word 0 Register
- * GMAC0 offset 0x8060
- * GMAC1 offset 0xC060
- */
-typedef union {
- unsigned int bits32;
- struct bit_8060 {
- unsigned int buffer_size : 16; /* bit 15:0 number of descriptors used for the current frame */
- unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
- unsigned int status : 4; /* bit 24:22 Status of rx frame */
- unsigned int chksum_status : 3; /* bit 28:26 Check Sum Status */
- unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
- unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
- unsigned int drop : 1; /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
- } bits;
-} GMAC_RXDESC_0_T;
-
-#define GMAC_RXDESC_0_T_derr BIT(30)
-#define GMAC_RXDESC_0_T_perr BIT(29)
-#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
-#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
-#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
-
-#define RX_CHKSUM_IP_UDP_TCP_OK 0
-#define RX_CHKSUM_IP_OK_ONLY 1
-#define RX_CHKSUM_NONE 2
-#define RX_CHKSUM_IP_ERR_UNKNOWN 4
-#define RX_CHKSUM_IP_ERR 5
-#define RX_CHKSUM_TCP_UDP_ERR 6
-#define RX_CHKSUM_NUM 8
-
-#define RX_STATUS_GOOD_FRAME 0
-#define RX_STATUS_TOO_LONG_GOOD_CRC 1
-#define RX_STATUS_RUNT_FRAME 2
-#define RX_STATUS_SFD_NOT_FOUND 3
-#define RX_STATUS_CRC_ERROR 4
-#define RX_STATUS_TOO_LONG_BAD_CRC 5
-#define RX_STATUS_ALIGNMENT_ERROR 6
-#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
-#define RX_STATUS_RX_ERR 8
-#define RX_STATUS_DA_FILTERED 9
-#define RX_STATUS_BUFFER_FULL 10
-#define RX_STATUS_NUM 16
-
-#define RX_ERROR_LENGTH(s) \
- ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
- (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
- (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
-#define RX_ERROR_OVER(s) \
- ((s) == RX_STATUS_BUFFER_FULL)
-#define RX_ERROR_CRC(s) \
- ((s) == RX_STATUS_CRC_ERROR || \
- (s) == RX_STATUS_TOO_LONG_BAD_CRC)
-#define RX_ERROR_FRAME(s) \
- ((s) == RX_STATUS_ALIGNMENT_ERROR || \
- (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
-#define RX_ERROR_FIFO(s) \
- (0)
-
-/*
- * GMAC DMA Rx Description Word 1 Register
- * GMAC0 offset 0x8064
- * GMAC1 offset 0xC064
- */
-typedef union {
- unsigned int bits32;
- struct rxdesc_word1 {
- unsigned int byte_count : 16; /* bit 15: 0 Rx Frame Byte Count */
- unsigned int sw_id : 16; /* bit 31:16 Software ID */
- } bits;
-} GMAC_RXDESC_1_T;
-
-/*
- * GMAC DMA Rx Description Word 2 Register
- * GMAC0 offset 0x8068
- * GMAC1 offset 0xC068
- */
-typedef union {
- unsigned int bits32;
- unsigned int buf_adr;
-} GMAC_RXDESC_2_T;
-
-#define RX_INSERT_NONE 0
-#define RX_INSERT_1_BYTE 1
-#define RX_INSERT_2_BYTE 2
-#define RX_INSERT_3_BYTE 3
-
-/*
- * GMAC DMA Rx Description Word 3 Register
- * GMAC0 offset 0x806C
- * GMAC1 offset 0xC06C
- */
-typedef union {
- unsigned int bits32;
- struct rxdesc_word3 {
- unsigned int l3_offset : 8; /* bit 7: 0 L3 data offset */
- unsigned int l4_offset : 8; /* bit 15: 8 L4 data offset */
- unsigned int l7_offset : 8; /* bit 23: 16 L7 data offset */
- unsigned int dup_ack : 1; /* bit 24 Duplicated ACK detected */
- unsigned int abnormal : 1; /* bit 25 abnormal case found */
- unsigned int option : 1; /* bit 26 IPV4 option or IPV6 extension header */
- unsigned int out_of_seq : 1; /* bit 27 Out of Sequence packet */
- unsigned int ctrl_flag : 1; /* bit 28 Control Flag is present */
- unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
- unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
- } bits;
-} GMAC_RXDESC_3_T;
-
-/*
- * GMAC Rx Descriptor
- */
-typedef struct {
- GMAC_RXDESC_0_T word0;
- GMAC_RXDESC_1_T word1;
- GMAC_RXDESC_2_T word2;
- GMAC_RXDESC_3_T word3;
-} GMAC_RXDESC_T;
-
-/*
- * GMAC Hash Engine Enable/Action Register 0 Offset Register
- * GMAC0 offset 0x8070
- * GMAC1 offset 0xC070
- */
-typedef union {
- unsigned int bits32;
- struct bit_8070 {
- unsigned int mr0hel : 6; /* bit 5:0 match rule 0 hash entry size */
- unsigned int mr0_action : 5; /* bit 10:6 Matching Rule 0 action offset */
- unsigned int reserved0 : 4; /* bit 14:11 */
- unsigned int mr0en : 1; /* bit 15 Enable Matching Rule 0 */
- unsigned int mr1hel : 6; /* bit 21:16 match rule 1 hash entry size */
- unsigned int mr1_action : 5; /* bit 26:22 Matching Rule 1 action offset */
- unsigned int timing : 3; /* bit 29:27 */
- unsigned int reserved1 : 1; /* bit 30 */
- unsigned int mr1en : 1; /* bit 31 Enable Matching Rule 1 */
- } bits;
-} GMAC_HASH_ENABLE_REG0_T;
-
-/*
- * GMAC Hash Engine Enable/Action Register 1 Offset Register
- * GMAC0 offset 0x8074
- * GMAC1 offset 0xC074
- */
-typedef union {
- unsigned int bits32;
- struct bit_8074 {
- unsigned int mr2hel : 6; /* bit 5:0 match rule 2 hash entry size */
- unsigned int mr2_action : 5; /* bit 10:6 Matching Rule 2 action offset */
- unsigned int reserved2 : 4; /* bit 14:11 */
- unsigned int mr2en : 1; /* bit 15 Enable Matching Rule 2 */
- unsigned int mr3hel : 6; /* bit 21:16 match rule 3 hash entry size */
- unsigned int mr3_action : 5; /* bit 26:22 Matching Rule 3 action offset */
- unsigned int reserved1 : 4; /* bit 30:27 */
- unsigned int mr3en : 1; /* bit 31 Enable Matching Rule 3 */
- } bits;
-} GMAC_HASH_ENABLE_REG1_T;
-
-/*
- * GMAC Matching Rule Control Register 0
- * GMAC0 offset 0x8078
- * GMAC1 offset 0xC078
- */
-typedef union {
- unsigned int bits32;
- struct bit_8078 {
- unsigned int sprx : 8; /* bit 7:0 Support Protocol Register 7:0 */
- unsigned int reserved2 : 4; /* bit 11:8 */
- unsigned int tos_traffic : 1; /* bit 12 IPV4 TOS or IPV6 Traffice Class */
- unsigned int flow_lable : 1; /* bit 13 IPV6 Flow label */
- unsigned int ip_hdr_len : 1; /* bit 14 IPV4 Header length */
- unsigned int ip_version : 1; /* bit 15 0: IPV4, 1: IPV6 */
- unsigned int reserved1 : 3; /* bit 18:16 */
- unsigned int pppoe : 1; /* bit 19 PPPoE Session ID enable */
- unsigned int vlan : 1; /* bit 20 VLAN ID enable */
- unsigned int ether_type : 1; /* bit 21 Ethernet type enable */
- unsigned int sa : 1; /* bit 22 MAC SA enable */
- unsigned int da : 1; /* bit 23 MAC DA enable */
- unsigned int priority : 3; /* bit 26:24 priority if multi-rules matched */
- unsigned int port : 1; /* bit 27 PORT ID matching enable */
- unsigned int l7 : 1; /* bit 28 L7 matching enable */
- unsigned int l4 : 1; /* bit 29 L4 matching enable */
- unsigned int l3 : 1; /* bit 30 L3 matching enable */
- unsigned int l2 : 1; /* bit 31 L2 matching enable */
- } bits;
-} GMAC_MRxCR0_T;
-
-#define MR_L2_BIT BIT(31)
-#define MR_L3_BIT BIT(30)
-#define MR_L4_BIT BIT(29)
-#define MR_L7_BIT BIT(28)
-#define MR_PORT_BIT BIT(27)
-#define MR_PRIORITY_BIT BIT(26)
-#define MR_DA_BIT BIT(23)
-#define MR_SA_BIT BIT(22)
-#define MR_ETHER_TYPE_BIT BIT(21)
-#define MR_VLAN_BIT BIT(20)
-#define MR_PPPOE_BIT BIT(19)
-#define MR_IP_VER_BIT BIT(15)
-#define MR_IP_HDR_LEN_BIT BIT(14)
-#define MR_FLOW_LABLE_BIT BIT(13)
-#define MR_TOS_TRAFFIC_BIT BIT(12)
-#define MR_SPR_BIT(x) BIT(x)
-#define MR_SPR_BITS 0xff
-
-/*
- * GMAC Matching Rule Control Register 1
- * GMAC0 offset 0x807C
- * GMAC1 offset 0xC07C
- */
-typedef union {
- unsigned int bits32;
- struct bit_807C {
- unsigned int l4_byte0_15 : 16; /* bit 15: 0 */
- unsigned int dip_netmask : 7; /* bit 22:16 Dest IP net mask, number of mask bits */
- unsigned int dip : 1; /* bit 23 Dest IP */
- unsigned int sip_netmask : 7; /* bit 30:24 Srce IP net mask, number of mask bits */
- unsigned int sip : 1; /* bit 31 Srce IP */
- } bits;
-} GMAC_MRxCR1_T;
-
-/*
- * GMAC Matching Rule Control Register 2
- * GMAC0 offset 0x8080
- * GMAC1 offset 0xC080
- */
-typedef union {
- unsigned int bits32;
- struct bit_8080 {
- unsigned int l7_byte0_23 : 24; /* bit 23:0 */
- unsigned int l4_byte16_24 : 8; /* bit 31: 24 */
- } bits;
-} GMAC_MRxCR2_T;
-
-/*
- * GMAC Support registers
- * GMAC0 offset 0x80A8
- * GMAC1 offset 0xC0A8
- */
-typedef union {
- unsigned int bits32;
- struct bit_80A8 {
- unsigned int protocol : 8; /* bit 7:0 Supported protocol */
- unsigned int swap : 3; /* bit 10:8 Swap */
- unsigned int reserved : 21; /* bit 31:11 */
- } bits;
-} GMAC_SPR_T;
-
-/*
- * GMAC_AHB_WEIGHT registers
- * GMAC0 offset 0x80C8
- * GMAC1 offset 0xC0C8
- */
-typedef union {
- unsigned int bits32;
- struct bit_80C8 {
- unsigned int hash_weight : 5; /* 4:0 */
- unsigned int rx_weight : 5; /* 9:5 */
- unsigned int tx_weight : 5; /* 14:10 */
- unsigned int pre_req : 5; /* 19:15 Rx Data Pre Request FIFO Threshold */
- unsigned int tqDV_threshold : 5; /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
- unsigned int reserved : 7; /* 31:25 */
- } bits;
-} GMAC_AHB_WEIGHT_T;
-
-/*
- * the register structure of GMAC
- */
-
-/*
- * GMAC RX FLTR
- * GMAC0 Offset 0xA00C
- * GMAC1 Offset 0xE00C
- */
-typedef union {
- unsigned int bits32;
- struct bit1_000c {
- unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
- unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
- unsigned int broadcast : 1; /* enable receive of broadcast frames */
- unsigned int promiscuous : 1; /* enable receive of all frames */
- unsigned int error : 1; /* enable receive of all error frames */
- unsigned int : 27;
- } bits;
-} GMAC_RX_FLTR_T;
-
-/*
- * GMAC Configuration 0
- * GMAC0 Offset 0xA018
- * GMAC1 Offset 0xE018
- */
-typedef union {
- unsigned int bits32;
- struct bit1_0018 {
- unsigned int dis_tx : 1; /* 0: disable transmit */
- unsigned int dis_rx : 1; /* 1: disable receive */
- unsigned int loop_back : 1; /* 2: transmit data loopback enable */
- unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
- unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
- unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
- unsigned int dis_bkoff : 1; /* 11: disable back-off function */
- unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
- unsigned int sim_test : 1; /* 13: speed up timers in simulation */
- unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
- unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
- unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
- unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
- unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
- unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
- unsigned int rgmm_edge : 1; /* 20 */
- unsigned int rxc_inv : 1; /* 21 */
- unsigned int ipv6_exthdr_order : 1; /* 22 */
- unsigned int rx_err_detect : 1; /* 23 */
- unsigned int port0_chk_hwq : 1; /* 24 */
- unsigned int port1_chk_hwq : 1; /* 25 */
- unsigned int port0_chk_toeq : 1; /* 26 */
- unsigned int port1_chk_toeq : 1; /* 27 */
- unsigned int port0_chk_classq : 1; /* 28 */
- unsigned int port1_chk_classq : 1; /* 29 */
- unsigned int reserved : 2; /* 31 */
- } bits;
-} GMAC_CONFIG0_T;
-
-#define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0))
-#define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17))
-#define CONFIG0_FLOW_RX (BIT(14))
-#define CONFIG0_FLOW_TX (BIT(15))
-#define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15))
-#define CONFIG0_FLOW_CTL (BIT(14)|BIT(15))
-
-#define CONFIG0_MAXLEN_SHIFT 8
-#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
-#define CONFIG0_MAXLEN_1536 0
-#define CONFIG0_MAXLEN_1518 1
-#define CONFIG0_MAXLEN_1522 2
-#define CONFIG0_MAXLEN_1542 3
-#define CONFIG0_MAXLEN_9k 4 /* 9212 */
-#define CONFIG0_MAXLEN_10k 5 /* 10236 */
-#define CONFIG0_MAXLEN_1518__6 6
-#define CONFIG0_MAXLEN_1518__7 7
-
-/*
- * GMAC Configuration 1
- * GMAC0 Offset 0xA01C
- * GMAC1 Offset 0xE01C
- */
-typedef union {
- unsigned int bits32;
- struct bit1_001c {
- unsigned int set_threshold : 8; /* flow control set threshold */
- unsigned int rel_threshold : 8; /* flow control release threshold */
- unsigned int reserved : 16;
- } bits;
-} GMAC_CONFIG1_T;
-
-#define GMAC_FLOWCTRL_SET_MAX 32
-#define GMAC_FLOWCTRL_SET_MIN 0
-#define GMAC_FLOWCTRL_RELEASE_MAX 32
-#define GMAC_FLOWCTRL_RELEASE_MIN 0
-
-/*
- * GMAC Configuration 2
- * GMAC0 Offset 0xA020
- * GMAC1 Offset 0xE020
- */
-typedef union {
- unsigned int bits32;
- struct bit1_0020 {
- unsigned int set_threshold : 16; /* flow control set threshold */
- unsigned int rel_threshold : 16; /* flow control release threshold */
- } bits;
-} GMAC_CONFIG2_T;
-
-/*
- * GMAC Configuration 3
- * GMAC0 Offset 0xA024
- * GMAC1 Offset 0xE024
- */
-typedef union {
- unsigned int bits32;
- struct bit1_0024 {
- unsigned int set_threshold : 16; /* flow control set threshold */
- unsigned int rel_threshold : 16; /* flow control release threshold */
- } bits;
-} GMAC_CONFIG3_T;
-
-
-/*
- * GMAC STATUS
- * GMAC0 Offset 0xA02C
- * GMAC1 Offset 0xE02C
- */
-typedef union {
- unsigned int bits32;
- struct bit1_002c {
- unsigned int link : 1; /* link status */
- unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
- unsigned int duplex : 1; /* duplex mode */
- unsigned int reserved : 1;
- unsigned int mii_rmii : 2; /* PHY interface type */
- unsigned int : 25;
- } bits;
-} GMAC_STATUS_T;
-
-#define GMAC_SPEED_10 0
-#define GMAC_SPEED_100 1
-#define GMAC_SPEED_1000 2
-
-#define GMAC_PHY_MII 0
-#define GMAC_PHY_GMII 1
-#define GMAC_PHY_RGMII_100_10 2
-#define GMAC_PHY_RGMII_1000 3
-
-/*
- * Queue Header
- * (1) TOE Queue Header
- * (2) Non-TOE Queue Header
- * (3) Interrupt Queue Header
- *
- * memory Layout
- * TOE Queue Header
- * 0x60003000 +---------------------------+ 0x0000
- * | TOE Queue 0 Header |
- * | 8 * 4 Bytes |
- * +---------------------------+ 0x0020
- * | TOE Queue 1 Header |
- * | 8 * 4 Bytes |
- * +---------------------------+ 0x0040
- * | ...... |
- * | |
- * +---------------------------+
- *
- * Non TOE Queue Header
- * 0x60002000 +---------------------------+ 0x0000
- * | Default Queue 0 Header |
- * | 2 * 4 Bytes |
- * +---------------------------+ 0x0008
- * | Default Queue 1 Header |
- * | 2 * 4 Bytes |
- * +---------------------------+ 0x0010
- * | Classification Queue 0 |
- * | 2 * 4 Bytes |
- * +---------------------------+
- * | Classification Queue 1 |
- * | 2 * 4 Bytes |
- * +---------------------------+ (n * 8 + 0x10)
- * | ... |
- * | 2 * 4 Bytes |
- * +---------------------------+ (13 * 8 + 0x10)
- * | Classification Queue 13 |
- * | 2 * 4 Bytes |
- * +---------------------------+ 0x80
- * | Interrupt Queue 0 |
- * | 2 * 4 Bytes |
- * +---------------------------+
- * | Interrupt Queue 1 |
- * | 2 * 4 Bytes |
- * +---------------------------+
- * | Interrupt Queue 2 |
- * | 2 * 4 Bytes |
- * +---------------------------+
- * | Interrupt Queue 3 |
- * | 2 * 4 Bytes |
- * +---------------------------+
- *
- */
-#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
-#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
-#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
-#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
-#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
-#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
-#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
-/*
- * TOE Queue Header Word 0
- */
-typedef union {
- unsigned int bits32;
- unsigned int base_size;
-} TOE_QHDR0_T;
-
-#define TOE_QHDR0_BASE_MASK (~0x0f)
-
-/*
- * TOE Queue Header Word 1
- */
-typedef union {
- unsigned int bits32;
- struct bit_qhdr1 {
- unsigned int rptr : 16; /* bit 15:0 */
- unsigned int wptr : 16; /* bit 31:16 */
- } bits;
-} TOE_QHDR1_T;
-
-/*
- * TOE Queue Header Word 2
- */
-typedef union {
- unsigned int bits32;
- struct bit_qhdr2 {
- unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
- unsigned int reserved : 7; /* bit 23:17 */
- unsigned int dack : 1; /* bit 24 1: Duplicated ACK */
- unsigned int abn : 1; /* bit 25 1: Abnormal case Found */
- unsigned int tcp_opt : 1; /* bit 26 1: Have TCP option */
- unsigned int ip_opt : 1; /* bit 27 1: have IPV4 option or IPV6 Extension header */
- unsigned int sat : 1; /* bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
- unsigned int osq : 1; /* bit 29 1: out of sequence */
- unsigned int ctl : 1; /* bit 30 1: have control flag bits (except ack) */
- unsigned int usd : 1; /* bit 31 0: if no data assembled yet */
- } bits;
-} TOE_QHDR2_T;
-
-/*
- * TOE Queue Header Word 3
- */
-typedef union {
- unsigned int bits32;
- unsigned int seq_num;
-} TOE_QHDR3_T;
-
-/*
- * TOE Queue Header Word 4
- */
-typedef union {
- unsigned int bits32;
- unsigned int ack_num;
-} TOE_QHDR4_T;
-
-/*
- * TOE Queue Header Word 5
- */
-typedef union {
- unsigned int bits32;
- struct bit_qhdr5 {
- unsigned int AckCnt : 16; /* bit 15:0 */
- unsigned int SeqCnt : 16; /* bit 31:16 */
- } bits;
-} TOE_QHDR5_T;
-
-/*
- * TOE Queue Header Word 6
- */
-typedef union {
- unsigned int bits32;
- struct bit_qhdr6 {
- unsigned int WinSize : 16; /* bit 15:0 */
- unsigned int iq_num : 2; /* bit 17:16 */
- unsigned int MaxPktSize : 14; /* bit 31:18 */
- } bits;
-} TOE_QHDR6_T;
-
-/*
- * TOE Queue Header Word 7
- */
-typedef union {
- unsigned int bits32;
- struct bit_qhdr7 {
- unsigned int AckThreshold : 16; /* bit 15:0 */
- unsigned int SeqThreshold : 16; /* bit 31:16 */
- } bits;
-} TOE_QHDR7_T;
-
-/*
- * TOE Queue Header
- */
-typedef struct {
- TOE_QHDR0_T word0;
- TOE_QHDR1_T word1;
- TOE_QHDR2_T word2;
- TOE_QHDR3_T word3;
- TOE_QHDR4_T word4;
- TOE_QHDR5_T word5;
- TOE_QHDR6_T word6;
- TOE_QHDR7_T word7;
-} TOE_QHDR_T;
-
-/*
- * NONTOE Queue Header Word 0
- */
-typedef union {
- unsigned int bits32;
- unsigned int base_size;
-} NONTOE_QHDR0_T;
-
-#define NONTOE_QHDR0_BASE_MASK (~0x0f)
-
-/*
- * NONTOE Queue Header Word 1
- */
-typedef union {
- unsigned int bits32;
- struct bit_nonqhdr1 {
- unsigned int rptr : 16; /* bit 15:0 */
- unsigned int wptr : 16; /* bit 31:16 */
- } bits;
-} NONTOE_QHDR1_T;
-
-/*
- * Non-TOE Queue Header
- */
-typedef struct {
- NONTOE_QHDR0_T word0;
- NONTOE_QHDR1_T word1;
-} NONTOE_QHDR_T;
-
-/*
- * Interrupt Queue Header Word 0
- */
-typedef union {
- unsigned int bits32;
- struct bit_intrqhdr0 {
- unsigned int win_size : 16; /* bit 15:0 Descriptor Ring Size */
- unsigned int wptr : 16; /* bit 31:16 Write Pointer where hw stopped */
- } bits;
-} INTR_QHDR0_T;
-
-/*
- * Interrupt Queue Header Word 1
- */
-typedef union {
- unsigned int bits32;
- struct bit_intrqhdr1 {
- unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
- unsigned int tcp_qid : 8; /* bit 24:17 TCP Queue ID */
- unsigned int dack : 1; /* bit 25 1: Duplicated ACK */
- unsigned int abn : 1; /* bit 26 1: Abnormal case Found */
- unsigned int tcp_opt : 1; /* bit 27 1: Have TCP option */
- unsigned int ip_opt : 1; /* bit 28 1: have IPV4 option or IPV6 Extension header */
- unsigned int sat : 1; /* bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
- unsigned int osq : 1; /* bit 30 1: out of sequence */
- unsigned int ctl : 1; /* bit 31 1: have control flag bits (except ack) */
- } bits;
-} INTR_QHDR1_T;
-
-/*
- * Interrupt Queue Header Word 2
- */
-typedef union {
- unsigned int bits32;
- unsigned int seq_num;
-} INTR_QHDR2_T;
-
-/*
- * Interrupt Queue Header Word 3
- */
-typedef union {
- unsigned int bits32;
- unsigned int ack_num;
-} INTR_QHDR3_T;
-
-/*
- * Interrupt Queue Header Word 4
- */
-typedef union {
- unsigned int bits32;
- struct bit_intrqhdr4 {
- unsigned int AckCnt : 16; /* bit 15:0 Ack# change since last ack# intr. */
- unsigned int SeqCnt : 16; /* bit 31:16 Seq# change since last seq# intr. */
- } bits;
-} INTR_QHDR4_T;
-
-/*
- * Interrupt Queue Header
- */
-typedef struct {
- INTR_QHDR0_T word0;
- INTR_QHDR1_T word1;
- INTR_QHDR2_T word2;
- INTR_QHDR3_T word3;
- INTR_QHDR4_T word4;
- unsigned int word5;
- unsigned int word6;
- unsigned int word7;
-} INTR_QHDR_T;
-
-#endif /* _GMAC_SL351x_H */
diff --git a/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c b/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c
deleted file mode 100644
index 0717abce9c48..000000000000
--- a/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Gemini EHCI Host Controller driver
- *
- * Copyright (C) 2014 Roman Yeryomin <***@advem.lv>
- * Copyright (C) 2012 Tobias Waldvogel
- * based on GPLd code from Sony Computer Entertainment Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- */
-#include <linux/kernel.h>
-#include <linux/hrtimer.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/usb.h>
-#include <linux/usb/hcd.h>
-#include <linux/usb/ehci_pdriver.h>
-
-#include <mach/hardware.h>
-#include <mach/global_reg.h>
-
-#include "ehci.h"
-
-#define DRV_NAME "ehci-fotg2"
-
-#define HCD_MISC 0x40
-
-#define OTGC_SCR 0x80
-#define OTGC_INT_STS 0x84
-#define OTGC_INT_EN 0x88
-
-#define GLOBAL_ISR 0xC0
-#define GLOBAL_ICR 0xC4
-
-#define GLOBAL_INT_POLARITY (1 << 3)
-#define GLOBAL_INT_MASK_HC (1 << 2)
-#define GLOBAL_INT_MASK_OTG (1 << 1)
-#define GLOBAL_INT_MASK_DEV (1 << 0)
-
-#define OTGC_SCR_ID (1 << 21)
-#define OTGC_SCR_CROLE (1 << 20)
-#define OTGC_SCR_VBUS_VLD (1 << 19)
-#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8)
-#define OTGC_SCR_A_SRP_DET_EN (1 << 7)
-#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6)
-#define OTGC_SCR_A_BUS_DROP (1 << 5)
-#define OTGC_SCR_A_BUS_REQ (1 << 4)
-
-#define OTGC_INT_APLGRMV (1 << 12)
-#define OTGC_INT_BPLGRMV (1 << 11)
-#define OTGC_INT_OVC (1 << 10)
-#define OTGC_INT_IDCHG (1 << 9)
-#define OTGC_INT_RLCHG (1 << 8)
-#define OTGC_INT_AVBUSERR (1 << 5)
-#define OTGC_INT_ASRPDET (1 << 4)
-#define OTGC_INT_BSRPDN (1 << 0)
-
-#define OTGC_INT_A_TYPE ( \
- OTGC_INT_ASRPDET | \
- OTGC_INT_AVBUSERR | \
- OTGC_INT_OVC | \
- OTGC_INT_RLCHG | \
- OTGC_INT_IDCHG | \
- OTGC_INT_APLGRMV \
- )
-#define OTGC_INT_B_TYPE ( \
- OTGC_INT_AVBUSERR | \
- OTGC_INT_OVC | \
- OTGC_INT_RLCHG | \
- OTGC_INT_IDCHG \
- )
-
-
-static void fotg2_otg_init(struct usb_hcd *hcd)
-{
- u32 val;
-
- writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
- GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
- hcd->regs + GLOBAL_ICR);
-
- val = readl(hcd->regs + OTGC_SCR);
- val &= ~(OTGC_SCR_A_SRP_RESP_TYPE | OTGC_SCR_A_SRP_DET_EN |
- OTGC_SCR_A_BUS_DROP | OTGC_SCR_A_SET_B_HNP_EN);
- val |= OTGC_SCR_A_BUS_REQ;
- writel(val, hcd->regs + OTGC_SCR);
-
- writel(OTGC_INT_A_TYPE, hcd->regs + OTGC_INT_EN);
-
- /* setup MISC register, fixes timing problems */
- val = readl(hcd->regs + HCD_MISC);
- val |= 0xD;
- writel(val, hcd->regs + HCD_MISC);
-
- writel(~0, hcd->regs + GLOBAL_ISR);
- writel(~0, hcd->regs + OTGC_INT_STS);
-}
-
-static int fotg2_ehci_reset(struct usb_hcd *hcd)
-{
- int retval;
-
- retval = ehci_setup(hcd);
- if (retval)
- return retval;
-
- writel(GLOBAL_INT_POLARITY, hcd->regs + GLOBAL_ICR);
- return 0;
-}
-
-static const struct hc_driver fotg2_ehci_hc_driver = {
- .description = hcd_name,
- .product_desc = "FOTG2 EHCI Host Controller",
- .hcd_priv_size = sizeof(struct ehci_hcd),
- .irq = ehci_irq,
- .flags = HCD_MEMORY | HCD_USB2,
- .reset = fotg2_ehci_reset,
- .start = ehci_run,
- .stop = ehci_stop,
- .shutdown = ehci_shutdown,
- .urb_enqueue = ehci_urb_enqueue,
- .urb_dequeue = ehci_urb_dequeue,
- .endpoint_disable = ehci_endpoint_disable,
- .endpoint_reset = ehci_endpoint_reset,
- .get_frame_number = ehci_get_frame,
- .hub_status_data = ehci_hub_status_data,
- .hub_control = ehci_hub_control,
-#if defined(CONFIG_PM)
- .bus_suspend = ehci_bus_suspend,
- .bus_resume = ehci_bus_resume,
-#endif
- .relinquish_port = ehci_relinquish_port,
- .port_handed_over = ehci_port_handed_over,
-
- .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
-};
-
-static irqreturn_t fotg2_ehci_irq(int irq, void *data)
-{
- struct usb_hcd *hcd = data;
- u32 icr, sts;
- irqreturn_t retval;
-
- icr = readl(hcd->regs + GLOBAL_ICR);
- writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
- GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
- hcd->regs + GLOBAL_ICR);
-
- retval = IRQ_NONE;
-
- sts = ~icr;
- sts &= GLOBAL_INT_MASK_HC | GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV;
- sts &= readl(hcd->regs + GLOBAL_ISR);
- writel(sts, hcd->regs + GLOBAL_ISR);
-
- if (unlikely(sts & GLOBAL_INT_MASK_DEV)) {
- ehci_warn(hcd_to_ehci(hcd),
- "Received unexpected irq for device role\n");
- retval = IRQ_HANDLED;
- }
-
- if (unlikely(sts & GLOBAL_INT_MASK_OTG)) {
- u32 otg_sts;
-
- otg_sts = readl(hcd->regs + OTGC_INT_STS);
- writel(otg_sts, hcd->regs + OTGC_INT_STS);
-
- ehci_warn(hcd_to_ehci(hcd),
- "Received unexpected irq for OTG management\n");
- retval = IRQ_HANDLED;
- }
-
- if (sts & GLOBAL_INT_MASK_HC) {
- retval = IRQ_NONE;
- }
-
- writel(icr, hcd->regs + GLOBAL_ICR);
- return retval;
-}
-
-static int fotg2_ehci_probe(struct platform_device *pdev)
-{
- struct usb_hcd *hcd;
- struct resource *res;
- int irq , err;
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- pr_err("no irq provided");
- return irq;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- pr_err("no memory resource provided");
- return -ENXIO;
- }
-
- hcd = usb_create_hcd(&fotg2_ehci_hc_driver, &pdev->dev,
- dev_name(&pdev->dev));
- if (!hcd)
- return -ENOMEM;
-
- hcd->rsrc_start = res->start;
- hcd->rsrc_len = resource_size(res);
-
- hcd->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(hcd->regs)) {
- err = -ENOMEM;
- goto err_put_hcd;
- }
-
- hcd->has_tt = 1;
- hcd_to_ehci(hcd)->caps = hcd->regs;
-
- fotg2_otg_init(hcd);
-
- err = request_irq(irq, &fotg2_ehci_irq, IRQF_SHARED, "fotg2", hcd);
- if (err)
- goto err_put_hcd;
-
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
- goto err_put_hcd;
-
- platform_set_drvdata(pdev, hcd);
- return 0;
-
-err_put_hcd:
- usb_put_hcd(hcd);
- return err;
-}
-
-static int fotg2_ehci_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
- writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC |
- GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV,
- hcd->regs + GLOBAL_ICR);
-
- free_irq(hcd->irq, hcd);
- usb_remove_hcd(hcd);
- usb_put_hcd(hcd);
- platform_set_drvdata(pdev, NULL);
-
- return 0;
-}
-
-MODULE_ALIAS("platform:" DRV_NAME);
-
-static struct platform_driver ehci_fotg2_driver = {
- .probe = fotg2_ehci_probe,
- .remove = fotg2_ehci_remove,
- .driver.name = DRV_NAME,
-};
diff --git a/target/linux/gemini/files/drivers/watchdog/gemini_wdt.c b/target/linux/gemini/files/drivers/watchdog/gemini_wdt.c
deleted file mode 100644
index 20d30b64eb35..000000000000
--- a/target/linux/gemini/files/drivers/watchdog/gemini_wdt.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Watchdog driver for Cortina Systems Gemini SoC
- *
- * Copyright (C) 2009 Paulius Zaleckas <***@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/platform_device.h>
-#include <linux/watchdog.h>
-#include <linux/slab.h>
-
-#define GEMINI_WDCOUNTER 0x0
-#define GEMINI_WDLOAD 0x4
-#define GEMINI_WDRESTART 0x8
-
-#define WDRESTART_MAGIC 0x5AB9
-
-#define GEMINI_WDCR 0xC
-
-#define WDCR_CLOCK_5MHZ (1 << 4)
-#define WDCR_SYS_RST (1 << 1)
-#define WDCR_ENABLE (1 << 0)
-
-#define WDT_CLOCK 5000000 /* 5 MHz */
-#define WDT_DEFAULT_TIMEOUT 13
-#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK)
-
-/* status bits */
-#define WDT_ACTIVE 0
-#define WDT_OK_TO_CLOSE 1
-
-static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
-static int nowayout = WATCHDOG_NOWAYOUT;
-
-static DEFINE_SPINLOCK(gemini_wdt_lock);
-
-static struct platform_device *gemini_wdt_dev;
-
-struct gemini_wdt_struct {
- struct resource *res;
- struct device *dev;
- void __iomem *base;
- unsigned long status;
-};
-
-static struct watchdog_info gemini_wdt_info = {
- .identity = "Gemini watchdog",
- .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
- WDIOF_SETTIMEOUT,
-};
-
-/* Disable the watchdog. */
-static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
-{
- spin_lock(&gemini_wdt_lock);
-
- __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
-
- clear_bit(WDT_ACTIVE, &gemini_wdt->status);
-
- spin_unlock(&gemini_wdt_lock);
-}
-
-/* Service the watchdog */
-static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
-{
- __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
-}
-
-/* Enable and reset the watchdog. */
-static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
-{
- spin_lock(&gemini_wdt_lock);
-
- __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
-
- gemini_wdt_service(gemini_wdt);
-
- /* set clock before enabling */
- __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
- gemini_wdt->base + GEMINI_WDCR);
-
- __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
- gemini_wdt->base + GEMINI_WDCR);
-
- set_bit(WDT_ACTIVE, &gemini_wdt->status);
-
- spin_unlock(&gemini_wdt_lock);
-}
-
-/* Watchdog device is opened, and watchdog starts running. */
-static int gemini_wdt_open(struct inode *inode, struct file *file)
-{
- struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
-
- if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
- return -EBUSY;
-
- file->private_data = gemini_wdt;
-
- gemini_wdt_start(gemini_wdt);
-
- return nonseekable_open(inode, file);
-}
-
-/* Close the watchdog device. */
-static int gemini_wdt_close(struct inode *inode, struct file *file)
-{
- struct gemini_wdt_struct *gemini_wdt = file->private_data;
-
- /* Disable the watchdog if possible */
- if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
- gemini_wdt_stop(gemini_wdt);
- else
- dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
-
- return 0;
-}
-
-/* Handle commands from user-space. */
-static long gemini_wdt_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- struct gemini_wdt_struct *gemini_wdt = file->private_data;
-
- int value;
-
- switch (cmd) {
- case WDIOC_KEEPALIVE:
- gemini_wdt_service(gemini_wdt);
- return 0;
-
- case WDIOC_GETSUPPORT:
- return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
- sizeof(gemini_wdt_info)) ? -EFAULT : 0;
-
- case WDIOC_SETTIMEOUT:
- if (get_user(value, (int *)arg))
- return -EFAULT;
-
- if ((value < 1) || (value > WDT_MAX_TIMEOUT))
- return -EINVAL;
-
- timeout = value;
-
- /* restart wdt to use new timeout */
- gemini_wdt_stop(gemini_wdt);
- gemini_wdt_start(gemini_wdt);
-
- /* Fall through */
- case WDIOC_GETTIMEOUT:
- return put_user(timeout, (int *)arg);
-
- case WDIOC_GETTIMELEFT:
- value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
- return put_user(value / WDT_CLOCK, (int *)arg);
-
- default:
- return -ENOTTY;
- }
-}
-
-/* Refresh the watchdog whenever device is written to. */
-static ssize_t gemini_wdt_write(struct file *file, const char *data,
- size_t len, loff_t *ppos)
-{
- struct gemini_wdt_struct *gemini_wdt = file->private_data;
-
- if (len) {
- if (!nowayout) {
- size_t i;
-
- clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
- for (i = 0; i != len; i++) {
- char c;
-
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- set_bit(WDT_OK_TO_CLOSE,
- &gemini_wdt->status);
- }
- }
- gemini_wdt_service(gemini_wdt);
- }
-
- return len;
-}
-
-static const struct file_operations gemini_wdt_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .unlocked_ioctl = gemini_wdt_ioctl,
- .open = gemini_wdt_open,
- .release = gemini_wdt_close,
- .write = gemini_wdt_write,
-};
-
-static struct miscdevice gemini_wdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &gemini_wdt_fops,
-};
-
-static void gemini_wdt_shutdown(struct platform_device *pdev)
-{
- struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-
- gemini_wdt_stop(gemini_wdt);
-}
-
-static int gemini_wdt_probe(struct platform_device *pdev)
-{
- int ret;
- int res_size;
- struct resource *res;
- void __iomem *base;
- struct gemini_wdt_struct *gemini_wdt;
- unsigned int reg;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&pdev->dev, "can't get device resources\n");
- return -ENODEV;
- }
-
- res_size = resource_size(res);
- if (!request_mem_region(res->start, res_size, res->name)) {
- dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
- res_size, res->start);
- return -ENOMEM;
- }
-
- base = ioremap(res->start, res_size);
- if (!base) {
- dev_err(&pdev->dev, "ioremap failed\n");
- ret = -EIO;
- goto fail0;
- }
-
- gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
- if (!gemini_wdt) {
- dev_err(&pdev->dev, "can't allocate interface\n");
- ret = -ENOMEM;
- goto fail1;
- }
-
- /* Setup gemini_wdt driver structure */
- gemini_wdt->base = base;
- gemini_wdt->res = res;
-
- /* Set up platform driver data */
- platform_set_drvdata(pdev, gemini_wdt);
- gemini_wdt_dev = pdev;
-
- if (gemini_wdt_miscdev.parent) {
- ret = -EBUSY;
- goto fail2;
- }
-
- gemini_wdt_miscdev.parent = &pdev->dev;
-
- reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
- if (reg & WDCR_ENABLE) {
- /* Watchdog was enabled by the bootloader, disable it. */
- reg &= ~(WDCR_ENABLE);
- __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
- }
-
- ret = misc_register(&gemini_wdt_miscdev);
- if (ret)
- goto fail2;
-
- return 0;
-
-fail2:
- platform_set_drvdata(pdev, NULL);
- kfree(gemini_wdt);
-fail1:
- iounmap(base);
-fail0:
- release_mem_region(res->start, res_size);
-
- return ret;
-}
-
-static int gemini_wdt_remove(struct platform_device *pdev)
-{
- struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
-
- platform_set_drvdata(pdev, NULL);
- misc_deregister(&gemini_wdt_miscdev);
- gemini_wdt_dev = NULL;
- iounmap(gemini_wdt->base);
- release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
-
- kfree(gemini_wdt);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-{
- struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
- unsigned int reg;
-
- reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
- reg &= ~(WDCR_WDENABLE);
- __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
-
- return 0;
-}
-
-static int gemini_wdt_resume(struct platform_device *pdev)
-{
- struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
- unsigned int reg;
-
- if (gemini_wdt->status) {
- reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
- reg |= WDCR_WDENABLE;
- __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
- }
-
- return 0;
-}
-#else
-#define gemini_wdt_suspend NULL
-#define gemini_wdt_resume NULL
-#endif
-
-static struct platform_driver gemini_wdt_driver = {
- .probe = gemini_wdt_probe,
- .remove = gemini_wdt_remove,
- .shutdown = gemini_wdt_shutdown,
- .suspend = gemini_wdt_suspend,
- .resume = gemini_wdt_resume,
- .driver = {
- .name = "gemini-wdt",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init gemini_wdt_init(void)
-{
- return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
-}
-
-static void __exit gemini_wdt_exit(void)
-{
- platform_driver_unregister(&gemini_wdt_driver);
-}
-
-module_init(gemini_wdt_init);
-module_exit(gemini_wdt_exit);
-
-module_param(timeout, uint, 0);
-MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
-
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
-
-MODULE_AUTHOR("Paulius Zaleckas");
-MODULE_DESCRIPTION("Watchdog driver for Gemini");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-MODULE_ALIAS("platform:gemini-wdt");
diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile
index 2cea85777041..e8bc5d3cb4c7 100644
--- a/target/linux/gemini/image/Makefile
+++ b/target/linux/gemini/image/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2009-2014 OpenWrt.org
+# Copyright (C) 2009-2018 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
@@ -7,81 +7,125 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk

-ifeq ($(SUBTARGET),wiligear)
-define Image/Prepare
-# WBD111: mach id 1690 (0x69a)
- echo -en "\x06\x1c\xa0\xe3\x9a\x10\x81\xe3" > $(KDIR)/wbd111-zImage
- cat $(KDIR)/zImage >> $(KDIR)/wbd111-zImage
-# WBD222: mach id 2753 (0xAC1)
- echo -en "\x0a\x1c\xa0\xe3\xc1\x10\x81\xe3" > $(KDIR)/wbd222-zImage
- cat $(KDIR)/zImage >> $(KDIR)/wbd222-zImage
+# Build the special D-Link DNS-313 header generator tool
+# needed to generate the hard disk boot images then
+# build D-Link DNS-313 images using the special header tool.
+# rootfs.tgz and rd.tgz contains nothing, we only need them
+# to satisfy the boot loader on the device. The zImage is
+# the only real content.
+define Build/dns313-images
+ if [ -d $(BIN_DIR)/.boot ] ; then rm -rf $(BIN_DIR)/.boot ; fi
+ mkdir -p $(BIN_DIR)/.boot
+ echo "dummy" > $(BIN_DIR)/.boot/dummyfile
+ dns313-header $(BIN_DIR)/.boot/dummyfile \
+ $(BIN_DIR)/.boot/rootfs.tgz
+ dns313-header $(BIN_DIR)/.boot/dummyfile \
+ $(BIN_DIR)/.boot/rd.gz
+ dns313-header $(IMAGE_KERNEL) \
+ $(BIN_DIR)/.boot/zImage
+ rm -f $(BIN_DIR)/.boot/dummyfile
+ (cd $(BIN_DIR); tar -czf $(IMG_PREFIX)-dns313-bootpart.tar.gz .boot)
+ if [ -d $(BIN_DIR)/.boot ] ; then rm -rf $(BIN_DIR)/.boot ; fi
endef
-endif

-ifeq ($(SUBTARGET),raidsonic)
-define Image/Prepare
-# NAS4220: mach id 2038 (0x7F6)
- echo -en "\x07\x1c\xa0\xe3\xf6\x10\x81\xe3" > $(KDIR)/nas4220-zImage
- cat $(KDIR)/zImage >> $(KDIR)/nas4220-zImage
+# Create the special NAS4220B image format with the squashfs
+# split across two "partitions" named rd.gz and hddapp.tgz but
+# essentially just being used by OpenWRT as one big partition
+define Build/nas4220b-images
+ dd if=$(IMAGE_ROOTFS) of=$(BIN_DIR)/rd.gz bs=6144k count=1
+ dd if=$(IMAGE_ROOTFS) of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1 seek=1
+ cp $(IMAGE_KERNEL) $(BIN_DIR)/zImage
+ cp ./ImageInfo-ib4220 $(BIN_DIR)/ImageInfo
+ (cd $(BIN_DIR); tar -czf $(IMG_PREFIX)-sysupgrade-ib4220b.tar.gz ImageInfo zImage rd.gz hddapp.tgz)
+ mv $(BIN_DIR)/rd.gz $(BIN_DIR)/$(IMG_PREFIX)-nas4220b-rd.gz
+ mv $(BIN_DIR)/hddapp.tgz $(BIN_DIR)/$(IMG_PREFIX)-nas4220b-hddapp.tgz
+ mv $(BIN_DIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-nas4220b-zImage
+ rm -f $(BIN_DIR)/ImageInfo
endef
-endif

-ifeq ($(SUBTARGET),wiligear)
-define Image/BuildKernel
-# workaround the bootloader's bug with extra nops
- echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
- cat $(KDIR)/wbd111-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
- echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
- cat $(KDIR)/wbd222-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
+# WBD-111 and WBD-222:
+# work around the bootloader's bug with extra nops
+# FIXME: is this really needed now that we no longer append the code
+# to change the machine ID number? Needs testing on Wiliboard.
+define Build/wbd-nops
+ mv $@ $@.tmp
+ echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $@
+ cat $@.tmp >> $@
+ rm -f $@.tmp
endef
-endif

-define Image/Build/jffs2-64k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync
+# All DTB files are prefixed with "gemini-"
+define Device/Default
+ DEVICE_DTS := $(patsubst %.dtb,%,$(notdir $(wildcard $(if $(IB),$(KDIR),$(DTS_DIR))/*-$(1).dtb)))
+ KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
+ KERNEL_NAME := zImage
+ KERNEL := kernel-bin | append-dtb
+ FILESYSTEMS := squashfs
+ IMAGE_NAME := $$(IMAGE_PREFIX)-$$(1).$$(2)
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
endef

-define Image/Build/jffs2-128k
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
+# A reasonable set of default packages handling the NAS type
+# of devices out of the box (former NAS32x0 IcyBox defaults)
+GEMINI_NAS_PACKAGES:=kmod-usb2 kmod-md-mod kmod-md-linear kmod-md-multipath \
+ kmod-md-raid0 kmod-md-raid1 kmod-md-raid10 kmod-md-raid456 \
+ kmod-fs-btrfs kmod-fs-cifs kmod-fs-ext4 kmod-fs-nfs \
+ kmod-fs-nfsd kmod-fs-ntfs kmod-fs-reiserfs kmod-fs-vfat \
+ kmod-nls-utf8 kmod-usb-storage-extras \
+ samba36-server mdadm cfdisk fdisk e2fsprogs badblocks
+
+DIR685_CMDLINE:=-console=ttyS0,19200n8 root=/dev/sda1 rw rootwait
+define Device/dlink-dir-685
+ DEVICE_TITLE := D-Link DIR-685 Xtreme N Storage Router
+ CMDLINE := $(DIR685_CMDLINE)
+ DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)
endef
+TARGET_DEVICES += dlink-dir-685

-define Image/Build/squashfs
- $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
- dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
+DNS313_CMDLINE:=-console=ttyS0,19200n8 root=/dev/sda4 rw rootwait
+define Device/dlink-dns-313
+ DEVICE_TITLE := D-Link DNS-313 1-Bay Network Storage Enclosure
+ CMDLINE := $(DNS313_CMDLINE)
+ DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)
+ IMAGES += dns313-image
+ IMAGE/dns313-image := dns313-images
endef
+TARGET_DEVICES += dlink-dns-313

-ifeq ($(SUBTARGET),wiligear)
-define Image/Build
- $(call Image/Build/$(1),$(1))
- -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
- -m GEOS -f 0x30000000 -z \
- -v WILI-S.WILIBOARD.v5.00.SL3512.OpenWrt.00000.000000.000000 \
- -o $(BIN_DIR)/$(IMG_PREFIX)-wbd111-$(1).bin \
- -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage \
- -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
+NAS4420B_CMDLINE:=-console=ttyS0,19200n8 root=/dev/mtd2 rw rootwait
+define Device/nas4220b
+ DEVICE_TITLE := Raidsonic NAS IB-4220-B
+ CMDLINE := $(NAS4420B_CMDLINE)
+ IMAGES += nas4220b-image
+ IMAGE/nas4220b-image := nas4220b-images
+endef
+TARGET_DEVICES += nas4220b

- -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
- -m GEOS -f 0x30000000 -z \
- -v WILI-S.WBD222.v5.00.SL3512.OpenWrt.00000.000000.000000 \
- -o $(BIN_DIR)/$(IMG_PREFIX)-wbd222-$(1).bin \
- -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage \
- -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
+define Device/rut1xx
+ DEVICE_TITLE := Teltonika RUT1xx
+ DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)
endef
-endif
+TARGET_DEVICES += rut1xx

-ifeq ($(SUBTARGET),raidsonic)
-define Image/Build
- $(call Image/Build/$(1),$(1))
- dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/rd.gz bs=6144k count=1
-# dd if=/dev/zero of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1
- dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1 seek=1
- cp $(KDIR)/nas4220-zImage $(BIN_DIR)/$(IMG_PREFIX)-nas4220-zImage
- cp $(BIN_DIR)/$(IMG_PREFIX)-nas4220-zImage $(BIN_DIR)/zImage
- cp ./ImageInfo-ib4220 $(BIN_DIR)/ImageInfo
- (cd $(BIN_DIR); tar -czf $(IMG_PREFIX)-sysupgrade-ib4220.tar.gz ImageInfo zImage rd.gz hddapp.tgz)
- mv $(BIN_DIR)/rd.gz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-rd.gz
- mv $(BIN_DIR)/hddapp.tgz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-hddapp.tgz
- rm -f $(BIN_DIR)/zImage $(BIN_DIR)/ImageInfo
+SQ201_CMDLINE:=-console=ttyS0,115200n8
+define Device/sq201
+ DEVICE_TITLE := ITian Square One SQ201
+ CMDLINE := $(SQ201_CMDLINE)
+ DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) rt61-pci-firmware
+endef
+TARGET_DEVICES += sq201
+
+define Device/wbd111
+ DEVICE_TITLE := Wiliboard WBD-111
+ KERNEL := kernel-bin | append-dtb | wbd-nops
+endef
+TARGET_DEVICES += wbd111
+
+define Device/wbd222
+ DEVICE_TITLE := Wiliboard WBD-222
+ KERNEL := kernel-bin | append-dtb | wbd-nops
endef
-endif
+TARGET_DEVICES += wbd222

$(eval $(call BuildImage))
diff --git a/target/linux/gemini/image/dns313-header/Makefile b/target/linux/gemini/image/dns313-header/Makefile
new file mode 100644
index 000000000000..ece48fd09d83
--- /dev/null
+++ b/target/linux/gemini/image/dns313-header/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2018 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+TARGET_DIR := $(KDIR)
+PKG_NAME := dns313-header
+PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)
+
+.PHONY : dns313-header-compile
+
+$(PKG_BUILD_DIR)/.prepared:
+ mkdir -p $(PKG_BUILD_DIR)
+ $(CP) ./dns313-header.c $(PKG_BUILD_DIR)/
+ touch $@
+
+download:
+
+prepare: $(PKG_BUILD_DIR)/.prepared
+
+compile: $(PKG_BUILD_DIR)/.prepared
+ $(CC) -o $(PKG_BUILD_DIR)/dns313-header \
+ $(PKG_BUILD_DIR)/dns313-header.c
+
+install:
+ cp $(PKG_BUILD_DIR)/dns313-header $(BIN_DIR)
+
+clean:
+ rm -rf $(PKG_BUILD_DIR)
diff --git a/target/linux/gemini/image/dns313-header/dns313-header.c b/target/linux/gemini/image/dns313-header/dns313-header.c
new file mode 100644
index 000000000000..e69e57e7baaa
--- /dev/null
+++ b/target/linux/gemini/image/dns313-header/dns313-header.c
@@ -0,0 +1,239 @@
+/*
+ * dns313-header.c
+ *
+ * Program to add the modified U-Boot header to a binary used with
+ * the D-Link DNS-313 boot loader when booting directly from an
+ * EXT2 formatted hard drive.
+ *
+ * The DNS313 use the same header on zImage, ramdisk, rootfs.
+ *
+ * Written by Linus Walleij <***@linaro.org>
+ * License terms: GPLv2
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+/*
+ * This is the U-Boot magic number, so the U-Boot header was used
+ * (obviously) as a template for this custom header.
+ */
+#define IH_MAGIC 0x27051956
+#define HEADER_SIZE 0x68
+
+#define OFFSET_MAGIC 0x00
+#define OFFSET_HCRC 0x04
+#define OFFSET_TIME 0x08
+#define OFFSET_SIZE 0x0c
+#define OFFSET_LOAD 0x10
+#define OFFSET_EP 0x14
+#define OFFSET_DCRC 0x18
+#define OFFSET_OS 0x1c
+#define OFFSET_ARCH 0x1d
+#define OFFSET_TYPE 0x1e
+#define OFFSET_COMP 0x1f
+#define OFFSET_NAME 0x20
+#define NAME_LEN 0x20
+#define OFFSET_MODEL 0x40
+#define MODEL_LEN 0x10
+#define OFFSET_VERSION 0x50
+#define VERSION_LEN 0x10
+#define OFFSET_MAC 0x60
+#define MAC_LEN 6
+
+static const uint32_t crc32_table[256] = {
+ 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL,
+ 0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL,
+ 0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL,
+ 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL,
+ 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL,
+ 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL,
+ 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL,
+ 0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL,
+ 0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL,
+ 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL,
+ 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL,
+ 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL,
+ 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL,
+ 0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL,
+ 0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL,
+ 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL,
+ 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL,
+ 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL,
+ 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL,
+ 0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL,
+ 0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL,
+ 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL,
+ 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL,
+ 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL,
+ 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL,
+ 0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL,
+ 0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL,
+ 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL,
+ 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL,
+ 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL,
+ 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL,
+ 0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL,
+ 0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL,
+ 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL,
+ 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL,
+ 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL,
+ 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL,
+ 0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL,
+ 0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL,
+ 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL,
+ 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL,
+ 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL,
+ 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL,
+ 0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL,
+ 0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL,
+ 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL,
+ 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL,
+ 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL,
+ 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL,
+ 0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL,
+ 0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL,
+ 0x2d02ef8dUL
+};
+
+static uint32_t crc32(uint32_t crc,
+ const unsigned char *buf,
+ unsigned int len)
+{
+ crc = crc ^ 0xffffffffUL;
+ do {
+ crc = crc32_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+ } while (--len);
+ return crc ^ 0xffffffffUL;
+}
+
+static void be_wr(unsigned char *buf, uint32_t val)
+{
+ buf[0] = (val >> 24) & 0xFFU;
+ buf[1] = (val >> 16) & 0xFFU;
+ buf[2] = (val >> 8) & 0xFFU;
+ buf[3] = val & 0xFFU;
+}
+
+int main(int argc, char **argv)
+{
+ int fdin;
+ int fdout;
+ struct stat sb;
+ uint32_t filesize;
+ uint32_t padding;
+ int ret = 0;
+ const char *pathin;
+ const char *pathout;
+ unsigned char *buffer;
+ unsigned char *infop;
+ uint32_t sum;
+ size_t bufsize;
+ size_t bytes;
+ int i;
+
+ if (argc < 3) {
+ printf("Too few arguments.\n");
+ printf("%s <infile> <outfile>\n", argv[0]);
+ }
+
+ pathin = argv[1];
+ pathout = argv[2];
+
+ ret = stat(pathin, &sb);
+ if (ret < 0)
+ return ret;
+
+ filesize = sb.st_size;
+ padding = filesize % 4;
+ printf("INFILE: %s, size: %08x bytes\n", pathin, filesize);
+ /* File + extended header size */
+ bufsize = filesize + HEADER_SIZE;
+
+ printf("Allocate %08x bytes\n", bufsize);
+ buffer = malloc(bufsize);
+ if (!buffer) {
+ printf("OOM: could not allocate buffer\n");
+ return 0;
+ }
+
+ memset(buffer, 0x00, bufsize);
+
+ /* Read file to buffer */
+ fdin = open(pathin, O_RDONLY);
+ if (!fdin) {
+ printf("ERROR: could not open input file\n");
+ return 0;
+ }
+ bytes = read(fdin, buffer + HEADER_SIZE, filesize);
+ if (bytes < filesize) {
+ printf("ERROR: could not read entire file\n");
+ return 0;
+ }
+ close(fdin);
+
+ /* PREP HEADER AND FOOTER */
+ infop = buffer;
+
+ be_wr(buffer + OFFSET_MAGIC, IH_MAGIC);
+
+ /* FIXME: use actual time */
+ be_wr(buffer + OFFSET_TIME, 0x4c06738c);
+ be_wr(buffer + OFFSET_SIZE, filesize);
+
+ /* Load address & entry point */
+ be_wr(buffer + OFFSET_LOAD, 0x00008000);
+ be_wr(buffer + OFFSET_EP, 0x00008000);
+
+ buffer[OFFSET_OS] = 0x05; /* Linux */
+ buffer[OFFSET_ARCH] = 0x02; /* ARM */
+ buffer[OFFSET_TYPE] = 0x02; /* OS kernel image */
+ buffer[OFFSET_COMP] = 0x01; /* gzip */
+
+ /* The vendor firmware just hardcodes this */
+ strncpy(buffer + OFFSET_NAME, "kernel.img", NAME_LEN);
+ buffer[OFFSET_NAME + NAME_LEN - 1] = '\0';
+ strncpy(buffer + OFFSET_MODEL, "dns-313v3", MODEL_LEN);
+ buffer[OFFSET_MODEL + MODEL_LEN - 1] = '\0';
+ strncpy(buffer + OFFSET_VERSION, "2.01b04", VERSION_LEN);
+ buffer[OFFSET_VERSION + VERSION_LEN - 1] = '\0';
+ /* Just some MAC address from the example */
+ buffer[OFFSET_MAC] = 0x00;
+ buffer[OFFSET_MAC + 1] = 0x80;
+ buffer[OFFSET_MAC + 2] = 0xc8;
+ buffer[OFFSET_MAC + 3] = 0x16;
+ buffer[OFFSET_MAC + 4] = 0x81;
+ buffer[OFFSET_MAC + 5] = 0x68;
+
+ /* Checksum payload */
+ sum = crc32(0, buffer + HEADER_SIZE, filesize);
+ be_wr(buffer + OFFSET_DCRC, sum);
+ printf("data checksum: 0x%08x\n", sum);
+
+ /* Checksum header, then write that into the header checksum */
+ sum = crc32(0, buffer, HEADER_SIZE);
+ be_wr(buffer + OFFSET_HCRC, sum);
+ printf("header checksum: 0x%08x\n", sum);
+
+ printf("OUTFILE: %s, size: %08x bytes\n", pathout, bufsize);
+ fdout = open(pathout, O_RDWR|O_CREAT|O_TRUNC,S_IRWXU|S_IRGRP);
+ if (!fdout) {
+ printf("ERROR: could not open output file\n");
+ return 0;
+ }
+ bytes = write(fdout, buffer, bufsize);
+ if (bytes < bufsize) {
+ printf("ERROR: could not write complete output file\n");
+ return 0;
+ }
+ close(fdout);
+
+ free(buffer);
+
+ return 0;
+}
diff --git a/target/linux/gemini/image/slask.mk b/target/linux/gemini/image/slask.mk
new file mode 100644
index 000000000000..3806be491587
--- /dev/null
+++ b/target/linux/gemini/image/slask.mk
@@ -0,0 +1,56 @@
+ifeq ($(SUBTARGET),wiligear)
+define Image/BuildKernel
+# workaround the bootloader's bug with extra nops
+ echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
+ cat $(KDIR)/wbd111-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage
+ echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
+ cat $(KDIR)/wbd222-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage
+endef
+endif
+
+define Image/Build/jffs2-64k
+ dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync
+endef
+
+define Image/Build/jffs2-128k
+ dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
+endef
+
+define Image/Build/squashfs
+ $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
+ dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync
+endef
+
+ifeq ($(SUBTARGET),wiligear)
+define Image/Build
+ $(call Image/Build/$(1),$(1))
+ -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
+ -m GEOS -f 0x30000000 -z \
+ -v WILI-S.WILIBOARD.v5.00.SL3512.OpenWrt.00000.000000.000000 \
+ -o $(BIN_DIR)/$(IMG_PREFIX)-wbd111-$(1).bin \
+ -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage \
+ -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
+
+ -$(STAGING_DIR_HOST)/bin/mkfwimage2 \
+ -m GEOS -f 0x30000000 -z \
+ -v WILI-S.WBD222.v5.00.SL3512.OpenWrt.00000.000000.000000 \
+ -o $(BIN_DIR)/$(IMG_PREFIX)-wbd222-$(1).bin \
+ -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage \
+ -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img
+endef
+endif
+
+ifeq ($(SUBTARGET),raidsonic)
+define Image/Build
+ $(call Image/Build/$(1),$(1))
+ dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/rd.gz bs=6144k count=1
+ dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1 seek=1
+ cp $(KDIR)/nas4220-zImage $(BIN_DIR)/$(IMG_PREFIX)-nas4220-zImage
+ cp $(BIN_DIR)/$(IMG_PREFIX)-nas4220-zImage $(BIN_DIR)/zImage
+ cp ./ImageInfo-ib4220 $(BIN_DIR)/ImageInfo
+ (cd $(BIN_DIR); tar -czf $(IMG_PREFIX)-sysupgrade-ib4220.tar.gz ImageInfo zImage rd.gz hddapp.tgz)
+ mv $(BIN_DIR)/rd.gz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-rd.gz
+ mv $(BIN_DIR)/hddapp.tgz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-hddapp.tgz
+ rm -f $(BIN_DIR)/zImage $(BIN_DIR)/ImageInfo
+endef
+endif
diff --git a/target/linux/gemini/raidsonic/config-default b/target/linux/gemini/raidsonic/config-default
deleted file mode 100644
index 91605238b43a..000000000000
--- a/target/linux/gemini/raidsonic/config-default
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=128M mtdparts=physmap-flash.0:128k(BOOT),3072k(Kern),6144k(Ramdisk),6144k(Application),128k(VCTL),640k(CurConf),128k(FIS-directory),***@0x320000(rootfs),***@0x20000(firmware) root=/dev/mtdblock7"
-CONFIG_MACH_NAS4220B=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_SPLIT_FIRMWARE=y
diff --git a/target/linux/gemini/raidsonic/target.mk b/target/linux/gemini/raidsonic/target.mk
deleted file mode 100644
index d158090d4db2..000000000000
--- a/target/linux/gemini/raidsonic/target.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-SUBTARGET:=raidsonic
-BOARDNAME:=Raidsonic NAS42x0
-FEATURES+=usb
-DEFAULT_PACKAGES+=kmod-usb2 kmod-md-mod kmod-md-linear kmod-md-multipath \
- kmod-md-raid0 kmod-md-raid1 kmod-md-raid10 kmod-md-raid456 \
- kmod-fs-btrfs kmod-fs-cifs kmod-fs-ext4 kmod-fs-nfs \
- kmod-fs-nfsd kmod-fs-ntfs kmod-fs-reiserfs kmod-fs-vfat \
- kmod-nls-utf8 kmod-usb-storage-extras \
- samba36-server mdadm cfdisk fdisk e2fsprogs badblocks
-
-define Target/Description
- Build firmware images for Raidsonic NAS4220.
-endef
diff --git a/target/linux/gemini/wiligear/target.mk b/target/linux/gemini/wiligear/target.mk
deleted file mode 100644
index 97cab18590cd..000000000000
--- a/target/linux/gemini/wiligear/target.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (C) 2014 OpenWrt.org
-#
-
-SUBTARGET:=wiligear
-BOARDNAME:=Wiligear WBD-222/111
-
-define Target/Description
- Build firmware images for Wiligear WBD-222 and WBD-111 boards.
-endef
--
2.14.3
Linus Walleij
2018-04-04 20:34:05 UTC
Permalink
This adds the patches to get fairly complete Gemini support
using kernel v4.14. It is mainly a backport of patches from
kernel v4.16 with omissions of things like graphics that require
substantial changes and will be better handled once we move
to the v4.16 kernel proper.

Signed-off-by: Linus Walleij <***@linaro.org>
---
target/linux/gemini/config-4.14 | 587 ++++
.../0001-cache-patch-from-OpenWRT.patch | 50 +
...0002-pinctrl-gemini-Add-missing-functions.patch | 33 +
...ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch | 51 +
...rl-Add-skew-delay-pin-config-and-bindings.patch | 73 +
...0005-pinctrl-gemini-Use-generic-DT-parser.patch | 112 +
...-gemini-Implement-clock-skew-delay-config.patch | 280 ++
.../0007-pinctrl-gemini-Fix-GMAC-groups.patch | 186 +
...nctrl-gemini-Fix-missing-pad-descriptions.patch | 27 +
...inctrl-gemini-Add-two-missing-GPIO-groups.patch | 25 +
...0-pinctrl-gemini-Fix-usage-of-3512-groups.patch | 25 +
...trl-gemini-Support-drive-strength-setting.patch | 198 ++
...d-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch | 113 +
...s-Add-basic-devicetree-for-D-Link-DNS-313.patch | 272 ++
...RM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch | 27 +
...0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch | 74 +
...-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch | 113 +
...tchdog-gemini-ftwdt010-rename-DT-bindings.patch | 88 +
...gemini-ftwdt010-rename-driver-and-symbols.patch | 527 +++
...watchdog-ftwdt010-Make-interrupt-optional.patch | 93 +
.../0020-soc-Add-SoC-driver-for-Gemini.patch | 113 +
...t-Add-DT-bindings-for-the-Gemini-ethernet.patch | 119 +
...t-Add-a-driver-for-Gemini-gigabit-etherne.patch | 3661 ++++++++++++++++++++
...23-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch | 74 +
.../0024-net-gemini-Depend-on-HAS_IOMEM.patch | 30 +
...-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch | 36 +
...r-gemini-poweroff-Avoid-spurious-poweroff.patch | 80 +
...sb-host-add-DT-bindings-for-faraday-fotg2.patch | 65 +
...28-usb-host-fotg2-add-device-tree-probing.patch | 61 +
...usb-host-fotg2-add-silicon-clock-handling.patch | 99 +
...b-host-fotg2-add-Gemini-specific-handling.patch | 131 +
...RM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch | 178 +
32 files changed, 7601 insertions(+)
create mode 100644 target/linux/gemini/config-4.14
create mode 100644 target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch
create mode 100644 target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch
create mode 100644 target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch
create mode 100644 target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch
create mode 100644 target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch
create mode 100644 target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch
create mode 100644 target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch
create mode 100644 target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch
create mode 100644 target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch
create mode 100644 target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch
create mode 100644 target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch
create mode 100644 target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch
create mode 100644 target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch
create mode 100644 target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch
create mode 100644 target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch
create mode 100644 target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch
create mode 100644 target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch
create mode 100644 target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch
create mode 100644 target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch
create mode 100644 target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch
create mode 100644 target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch
create mode 100644 target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch
create mode 100644 target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch
create mode 100644 target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch
create mode 100644 target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch
create mode 100644 target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch
create mode 100644 target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch
create mode 100644 target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch

diff --git a/target/linux/gemini/config-4.14 b/target/linux/gemini/config-4.14
new file mode 100644
index 000000000000..a01232eba1a9
--- /dev/null
+++ b/target/linux/gemini/config-4.14
@@ -0,0 +1,587 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMBA_PL08X=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_GEMINI=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MOXART is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+# CONFIG_ARCH_MULTI_V5 is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BOUNCE=y
+# CONFIG_BPF_SYSCALL is not set
+# CONFIG_BRIDGE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,19200n8"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_GEMINI=y
+CONFIG_COMPACTION=y
+CONFIG_COMPAT_BRK=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_FA=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FA=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_FA526=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_TLB_FA=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+# CONFIG_DMA_NOOP_OPS is not set
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+# CONFIG_DMA_VIRT_OPS is not set
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_LIB_RANDOM is not set
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DST_CACHE=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_EXPERT is not set
+CONFIG_EXPORTFS=y
+CONFIG_EXT4_FS=y
+CONFIG_FARADAY_FTINTC010=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTTMR010_TIMER=y
+CONFIG_FTWDT010_WATCHDOG=y
+CONFIG_FUTEX_PI=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GEMINI_ETHERNET=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INITRAMFS_FORCE is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_MCE_KBD_DECODER=y
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_SANYO_DECODER=y
+CONFIG_IR_SHARP_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+CONFIG_IR_XMP_DECODER=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_DLINK_DIR685=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LIBFDT=y
+# CONFIG_LIRC is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_GPIO=y
+# CONFIG_MEMCG is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF_GEMINI=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_DSA=y
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_NS=y
+CONFIG_NET_PACKET_ENGINE=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NET_VENDOR_CORTINA=y
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_OABI_COMPAT=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OVERLAY_FS=y
+# CONFIG_PACKET is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PATA_FTIDE010=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GEMINI=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GEMINI_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_QTNFMAC_PEARL_PCIE is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RC_CORE=y
+CONFIG_RC_DECODERS=y
+# CONFIG_RC_DEVICES is not set
+CONFIG_RC_MAP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_FTRTC010=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_GEMINI=y
+CONFIG_SATA_PMP=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_SQUASHFS is not set
+CONFIG_SRCU=y
+# CONFIG_STAGING is not set
+# CONFIG_STRICT_KERNEL_RWX is not set
+# CONFIG_STRICT_MODULE_RWX is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKS_RCU=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THIN_ARCHIVES=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUN=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_FOTG210_HCD=y
+CONFIG_USB_HID=y
+CONFIG_USB_MON=y
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=y
+# CONFIG_USERIO is not set
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFAT_FS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VLAN_8021Q is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_WLAN_VENDOR_RALINK=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch b/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch
new file mode 100644
index 000000000000..4430ffee9d74
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch
@@ -0,0 +1,50 @@
+From 57615e112aba6ae4c831d50e769c2c102f013686 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Tue, 7 Jun 2016 22:53:24 +0200
+Subject: [PATCH 01/31] cache patch from OpenWRT
+
+---
+ arch/arm/mm/cache-fa.S | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/mm/cache-fa.S
++++ b/arch/arm/mm/cache-fa.S
+@@ -24,7 +24,8 @@
+ /*
+ * The size of one data cache line.
+ */
+-#define CACHE_DLINESIZE 16
++#define CACHE_DLINESIZE 16
++#define CACHE_DLINESHIFT 4
+
+ /*
+ * The total size of the data cache.
+@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
+ * - start - virtual start address
+ * - end - virtual end address
+ */
++__flush_whole_dcache:
++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
++ mov r0, #0
++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
++ mov pc, lr
++
+ fa_dma_inv_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ tst r0, #CACHE_DLINESIZE - 1
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
+@@ -193,6 +204,10 @@ fa_dma_inv_range:
+ * - end - virtual end address
+ */
+ fa_dma_clean_range:
++ sub r3, r1, r0 @ calculate total size
++ cmp r3, #CACHE_DLIMIT @ total size >= limit?
++ bhs __flush_whole_dcache @ flush whole D cache
++
+ bic r0, r0, #CACHE_DLINESIZE - 1
+ 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
+ add r0, r0, #CACHE_DLINESIZE
diff --git a/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch b/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch
new file mode 100644
index 000000000000..604fee469c79
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0002-pinctrl-gemini-Add-missing-functions.patch
@@ -0,0 +1,33 @@
+From fd7823e6993f440930e9cb85e56375be5823485c Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 14 Oct 2017 17:13:03 +0200
+Subject: [PATCH 02/31] pinctrl: gemini: Add missing functions
+
+Some two functions were missing from the Gemini pin control
+driver. Noticed when trying to use ethernet. Fix it up by
+adding them.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2074,6 +2074,16 @@ static const struct gemini_pmx_func gemi
+ .num_groups = ARRAY_SIZE(satagrps),
+ },
+ {
++ .name = "usb",
++ .groups = usbgrps,
++ .num_groups = ARRAY_SIZE(usbgrps),
++ },
++ {
++ .name = "gmii",
++ .groups = gmiigrps,
++ .num_groups = ARRAY_SIZE(gmiigrps),
++ },
++ {
+ .name = "pci",
+ .groups = pcigrps,
+ .num_groups = ARRAY_SIZE(pcigrps),
diff --git a/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch b/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch
new file mode 100644
index 000000000000..81d9788af0bf
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch
@@ -0,0 +1,51 @@
+From 00e53d08bbe92051765c5bb94223b6f628cd3740 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Wed, 11 Oct 2017 19:45:19 +0200
+Subject: [PATCH 03/31] ARM: dts: Add TVE200 to the Gemini SoC DTSI
+
+The Faraday TVE200 is present in the Gemini SoC, sometimes
+under the name "TVC". Add it to the SoC DTSI file along with
+its resources.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+Signed-off-by: Arnd Bergmann <***@arndb.de>
+---
+ arch/arm/boot/dts/gemini.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -142,6 +142,12 @@
+ groups = "idegrp";
+ };
+ };
++ tvc_default_pins: pinctrl-tvc {
++ mux {
++ function = "tvc";
++ groups = "tvcgrp";
++ };
++ };
+ };
+ };
+
+@@ -348,5 +354,20 @@
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
++
++ display-***@6a000000 {
++ compatible = "cortina,gemini-tvc", "faraday,tve200";
++ reg = <0x6a000000 0x1000>;
++ interrupts = <13 IRQ_TYPE_EDGE_RISING>;
++ resets = <&syscon GEMINI_RESET_TVC>;
++ clocks = <&syscon GEMINI_CLK_GATE_TVC>,
++ <&syscon GEMINI_CLK_TVC>;
++ clock-names = "PCLK", "TVE";
++ pinctrl-names = "default";
++ pinctrl-0 = <&tvc_default_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
+ };
+ };
diff --git a/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch b/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch
new file mode 100644
index 000000000000..ac39a3282dc9
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch
@@ -0,0 +1,73 @@
+From eb3742c4250c6a79e7080bdb6286e5df50c7f26a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:17 +0200
+Subject: [PATCH 04/31] pinctrl: Add skew-delay pin config and bindings
+
+Some pin controllers (such as the Gemini) can control the
+expected clock skew and output delay on certain pins with a
+sub-nanosecond granularity. This is typically done by shunting
+in a number of double inverters in front of or behind the pin.
+Make it possible to configure this with a generic binding.
+
+Cc: ***@vger.kernel.org
+Acked-by: Rob Herring <***@kernel.org>
+Acked-by: Hans Ulli Kroll <***@googlemail.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 4 ++++
+ drivers/pinctrl/pinconf-generic.c | 2 ++
+ include/linux/pinctrl/pinconf-generic.h | 5 +++++
+ 3 files changed, 11 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
++++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+@@ -271,6 +271,10 @@ output-high - set the pin to output mod
+ sleep-hardware-state - indicate this is sleep related state which will be programmed
+ into the registers for the sleep state.
+ slew-rate - set the slew rate
++skew-delay - this affects the expected clock skew on input pins
++ and the delay before latching a value to an output
++ pin. Typically indicates how many double-inverters are
++ used to delay the signal.
+
+ For example:
+
+--- a/drivers/pinctrl/pinconf-generic.c
++++ b/drivers/pinctrl/pinconf-generic.c
+@@ -49,6 +49,7 @@ static const struct pin_config_item conf
+ PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
+ PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
+ PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
++ PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
+ };
+
+ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
+@@ -181,6 +182,7 @@ static const struct pinconf_generic_para
+ { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
+ { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
++ { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
+ };
+
+ /**
+--- a/include/linux/pinctrl/pinconf-generic.h
++++ b/include/linux/pinctrl/pinconf-generic.h
+@@ -90,6 +90,10 @@
+ * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
+ * this parameter (on a custom format) tells the driver which alternative
+ * slew rate to use.
++ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
++ * or latch delay (on outputs) this parameter (in a custom format)
++ * specifies the clock skew or latch delay. It typically controls how
++ * many double inverters are put in front of the line.
+ * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ * you need to pass in custom configurations to the pin controller, use
+ * PIN_CONFIG_END+1 as the base offset.
+@@ -117,6 +121,7 @@ enum pin_config_param {
+ PIN_CONFIG_POWER_SOURCE,
+ PIN_CONFIG_SLEEP_HARDWARE_STATE,
+ PIN_CONFIG_SLEW_RATE,
++ PIN_CONFIG_SKEW_DELAY,
+ PIN_CONFIG_END = 0x7F,
+ PIN_CONFIG_MAX = 0xFF,
+ };
diff --git a/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch b/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch
new file mode 100644
index 000000000000..5b0bba1cd4a6
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0005-pinctrl-gemini-Use-generic-DT-parser.patch
@@ -0,0 +1,112 @@
+From 09240ae27ffca65518f7b9d2360c020c1b1ddabe Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:18 +0200
+Subject: [PATCH 05/31] pinctrl: gemini: Use generic DT parser
+
+We can just use the generic Device Tree parser code
+in this driver and save some code.
+
+Acked-by: Hans Ulli Kroll <***@googlemail.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/Kconfig | 1 +
+ drivers/pinctrl/pinctrl-gemini.c | 66 +++-------------------------------------
+ 2 files changed, 5 insertions(+), 62 deletions(-)
+
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -153,6 +153,7 @@ config PINCTRL_GEMINI
+ depends on ARCH_GEMINI
+ default ARCH_GEMINI
+ select PINMUX
++ select GENERIC_PINCONF
+ select MFD_SYSCON
+
+ config PINCTRL_MCP23S08
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -13,6 +13,8 @@
+ #include <linux/pinctrl/machine.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ #include <linux/regmap.h>
+@@ -1918,73 +1920,13 @@ static void gemini_pin_dbg_show(struct p
+ seq_printf(s, " " DRIVER_NAME);
+ }
+
+-static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+- struct device_node *np,
+- struct pinctrl_map **map,
+- unsigned int *reserved_maps,
+- unsigned int *num_maps)
+-{
+- int ret;
+- const char *function = NULL;
+- const char *group;
+- struct property *prop;
+-
+- ret = of_property_read_string(np, "function", &function);
+- if (ret < 0)
+- return ret;
+-
+- ret = of_property_count_strings(np, "groups");
+- if (ret < 0)
+- return ret;
+-
+- ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
+- num_maps, ret);
+- if (ret < 0)
+- return ret;
+-
+- of_property_for_each_string(np, "groups", prop, group) {
+- ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps,
+- num_maps, group, function);
+- if (ret < 0)
+- return ret;
+- pr_debug("ADDED FUNCTION %s <-> GROUP %s\n",
+- function, group);
+- }
+-
+- return 0;
+-}
+-
+-static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+- struct device_node *np_config,
+- struct pinctrl_map **map,
+- unsigned int *num_maps)
+-{
+- unsigned int reserved_maps = 0;
+- struct device_node *np;
+- int ret;
+-
+- *map = NULL;
+- *num_maps = 0;
+-
+- for_each_child_of_node(np_config, np) {
+- ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map,
+- &reserved_maps, num_maps);
+- if (ret < 0) {
+- pinctrl_utils_free_map(pctldev, *map, *num_maps);
+- return ret;
+- }
+- }
+-
+- return 0;
+-};
+-
+ static const struct pinctrl_ops gemini_pctrl_ops = {
+ .get_groups_count = gemini_get_groups_count,
+ .get_group_name = gemini_get_group_name,
+ .get_group_pins = gemini_get_group_pins,
+ .pin_dbg_show = gemini_pin_dbg_show,
+- .dt_node_to_map = gemini_pinctrl_dt_node_to_map,
+- .dt_free_map = pinctrl_utils_free_map,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
++ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
+ /**
diff --git a/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch b/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch
new file mode 100644
index 000000000000..4bff3bce9c21
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0006-pinctrl-gemini-Implement-clock-skew-delay-config.patch
@@ -0,0 +1,280 @@
+From 43e8f011ddbb293e0a3394d0f39819ea2ead4a1b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 28 Oct 2017 15:37:19 +0200
+Subject: [PATCH 06/31] pinctrl: gemini: Implement clock skew/delay config
+
+This enabled pin config on the Gemini driver and implements
+pin skew/delay so that the ethernet pins clocking can be
+properly configured.
+
+Acked-by: Hans Ulli Kroll <***@googlemail.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 10 +-
+ drivers/pinctrl/pinctrl-gemini.c | 178 ++++++++++++++++++++-
+ 2 files changed, 182 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+@@ -9,8 +9,14 @@ The pin controller node must be a subnod
+ Required properties:
+ - compatible: "cortina,gemini-pinctrl"
+
+-Subnodes of the pin controller contain pin control multiplexing set-up.
+-Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
++Subnodes of the pin controller contain pin control multiplexing set-up
++and pin configuration of individual pins.
++
++Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
++and generic pin config nodes.
++
++Supported configurations:
++- skew-delay is supported on the Ethernet pins
+
+ Example:
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -24,6 +24,19 @@
+ #define DRIVER_NAME "pinctrl-gemini"
+
+ /**
++ * struct gemini_pin_conf - information about configuring a pin
++ * @pin: the pin number
++ * @reg: config register
++ * @mask: the bits affecting the configuration of the pin
++ */
++struct gemini_pin_conf {
++ unsigned int pin;
++ u32 reg;
++ u32 mask;
++};
++
++/**
++ * struct gemini_pmx - state holder for the gemini pin controller
+ * @dev: a pointer back to containing device
+ * @virtbase: the offset to the controller in virtual memory
+ * @map: regmap to access registers
+@@ -31,6 +44,8 @@
+ * @is_3516: whether the SoC/package is the 3516 variant
+ * @flash_pin: whether the flash pin (extended pins for parallel
+ * flash) is set
++ * @confs: pin config information
++ * @nconfs: number of pin config information items
+ */
+ struct gemini_pmx {
+ struct device *dev;
+@@ -39,6 +54,8 @@ struct gemini_pmx {
+ bool is_3512;
+ bool is_3516;
+ bool flash_pin;
++ const struct gemini_pin_conf *confs;
++ unsigned int nconfs;
+ };
+
+ /**
+@@ -59,6 +76,13 @@ struct gemini_pin_group {
+ u32 value;
+ };
+
++/* Some straight-forward control registers */
++#define GLOBAL_WORD_ID 0x00
++#define GLOBAL_STATUS 0x04
++#define GLOBAL_STATUS_FLPIN BIT(20)
++#define GLOBAL_GMAC_CTRL_SKEW 0x1c
++#define GLOBAL_GMAC0_DATA_SKEW 0x20
++#define GLOBAL_GMAC1_DATA_SKEW 0x24
+ /*
+ * Global Miscellaneous Control Register
+ * This register controls all Gemini pad/pin multiplexing
+@@ -71,9 +95,6 @@ struct gemini_pin_group {
+ * DISABLED again. So you select a flash configuration once, and then
+ * you are stuck with it.
+ */
+-#define GLOBAL_WORD_ID 0x00
+-#define GLOBAL_STATUS 0x04
+-#define GLOBAL_STATUS_FLPIN BIT(20)
+ #define GLOBAL_MISC_CTRL 0x30
+ #define TVC_CLK_PAD_ENABLE BIT(20)
+ #define PCI_CLK_PAD_ENABLE BIT(17)
+@@ -1925,7 +1946,7 @@ static const struct pinctrl_ops gemini_p
+ .get_group_name = gemini_get_group_name,
+ .get_group_pins = gemini_get_group_pins,
+ .pin_dbg_show = gemini_pin_dbg_show,
+- .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinconf_generic_dt_free_map,
+ };
+
+@@ -2203,10 +2224,155 @@ static const struct pinmux_ops gemini_pm
+ .set_mux = gemini_pmx_set_mux,
+ };
+
++#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
++ .pin = _n, \
++ .reg = _r, \
++ .mask = GENMASK(_hb, _lb) \
++}
++
++static const struct gemini_pin_conf gemini_confs_3512[] = {
++ GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
++ GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
++ GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
++ GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
++ GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
++ GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
++ GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
++ GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
++ GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
++ GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
++ GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
++ GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
++ GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
++ GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
++ GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
++ GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
++ GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
++ GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
++ GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
++ GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
++ GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
++ GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
++ GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
++ GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
++};
++
++static const struct gemini_pin_conf gemini_confs_3516[] = {
++ GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
++ GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
++ GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
++ GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
++ GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
++ GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
++ GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
++ GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
++ GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
++ GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
++ GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
++ GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
++ GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
++ GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
++ GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
++ GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
++ GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
++ GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
++ GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
++ GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
++ GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
++ GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
++ GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
++ GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
++};
++
++static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
++ unsigned int pin)
++{
++ const struct gemini_pin_conf *retconf;
++ int i;
++
++ for (i = 0; i < pmx->nconfs; i++) {
++ retconf = &gemini_confs_3516[i];
++ if (retconf->pin == pin)
++ return retconf;
++ }
++ return NULL;
++}
++
++static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *config)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ enum pin_config_param param = pinconf_to_config_param(*config);
++ const struct gemini_pin_conf *conf;
++ u32 val;
++
++ switch (param) {
++ case PIN_CONFIG_SKEW_DELAY:
++ conf = gemini_get_pin_conf(pmx, pin);
++ if (!conf)
++ return -ENOTSUPP;
++ regmap_read(pmx->map, conf->reg, &val);
++ val &= conf->mask;
++ val >>= (ffs(conf->mask) - 1);
++ *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++
++ return 0;
++}
++
++static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *configs, unsigned int num_configs)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ const struct gemini_pin_conf *conf;
++ enum pin_config_param param;
++ u32 arg;
++ int ret = 0;
++ int i;
++
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ arg = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_SKEW_DELAY:
++ if (arg > 0xf)
++ return -EINVAL;
++ conf = gemini_get_pin_conf(pmx, pin);
++ if (!conf) {
++ dev_err(pmx->dev,
++ "invalid pin for skew delay %d\n", pin);
++ return -ENOTSUPP;
++ }
++ arg <<= (ffs(conf->mask) - 1);
++ dev_dbg(pmx->dev,
++ "set pin %d to skew delay mask %08x, val %08x\n",
++ pin, conf->mask, arg);
++ regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
++ break;
++ default:
++ dev_err(pmx->dev, "Invalid config param %04x\n", param);
++ return -ENOTSUPP;
++ }
++ }
++
++ return ret;
++}
++
++static const struct pinconf_ops gemini_pinconf_ops = {
++ .pin_config_get = gemini_pinconf_get,
++ .pin_config_set = gemini_pinconf_set,
++ .is_generic = true,
++};
++
+ static struct pinctrl_desc gemini_pmx_desc = {
+ .name = DRIVER_NAME,
+ .pctlops = &gemini_pctrl_ops,
+ .pmxops = &gemini_pmx_ops,
++ .confops = &gemini_pinconf_ops,
+ .owner = THIS_MODULE,
+ };
+
+@@ -2249,11 +2415,15 @@ static int gemini_pmx_probe(struct platf
+ val &= 0xffff;
+ if (val == 0x3512) {
+ pmx->is_3512 = true;
++ pmx->confs = gemini_confs_3512;
++ pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
+ gemini_pmx_desc.pins = gemini_3512_pins;
+ gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
+ dev_info(dev, "detected 3512 chip variant\n");
+ } else if (val == 0x3516) {
+ pmx->is_3516 = true;
++ pmx->confs = gemini_confs_3516;
++ pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
+ gemini_pmx_desc.pins = gemini_3516_pins;
+ gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
+ dev_info(dev, "detected 3516 chip variant\n");
diff --git a/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch b/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch
new file mode 100644
index 000000000000..902168ba62a0
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0007-pinctrl-gemini-Fix-GMAC-groups.patch
@@ -0,0 +1,186 @@
+From e7759c44e0c20dd6b5a259300acdc7350ea6dd32 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 6 Nov 2017 21:27:34 +0100
+Subject: [PATCH 07/31] pinctrl: gemini: Fix GMAC groups
+
+The GMII groups need to be split across GMAC0 and GMAC1 since
+GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7
+so we might want just one interface out.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++-------------
+ 1 file changed, 54 insertions(+), 25 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -96,6 +96,13 @@ struct gemini_pin_group {
+ * you are stuck with it.
+ */
+ #define GLOBAL_MISC_CTRL 0x30
++#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
++/* Not really used */
++#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
++/* Activated with GMAC1 */
++#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
++/* This will be the default */
++#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
+ #define TVC_CLK_PAD_ENABLE BIT(20)
+ #define PCI_CLK_PAD_ENABLE BIT(17)
+ #define LPC_CLK_PAD_ENABLE BIT(16)
+@@ -109,8 +116,8 @@ struct gemini_pin_group {
+ #define NAND_PADS_DISABLE BIT(2)
+ #define PFLASH_PADS_DISABLE BIT(1)
+ #define SFLASH_PADS_DISABLE BIT(0)
+-#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
+-#define PADS_MAXBIT 20
++#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
++#define PADS_MAXBIT 27
+
+ /* Ordered by bit index */
+ static const char * const gemini_padgroups[] = {
+@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[
+ };
+
+ /* GMII, ethernet pins */
+-static const unsigned int gmii_3512_pins[] = {
+- 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
+- 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
++static const unsigned int gmii_gmac0_3512_pins[] = {
++ 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
++};
++
++static const unsigned int gmii_gmac1_3512_pins[] = {
++ 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
+ };
+
+ static const unsigned int pci_3512_pins[] = {
+@@ -668,10 +678,10 @@ static const unsigned int gpio1c_3512_pi
+ /* The GPIO1D (28-31) pins overlap with LCD and TVC */
+ static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
+
+-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
++/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
+ static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
+
+-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
++/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
+ static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
+
+ /* The GPIO2C (8-31) pins overlap with PCI */
+@@ -738,9 +748,16 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(usb_3512_pins),
+ },
+ {
+- .name = "gmiigrp",
+- .pins = gmii_3512_pins,
+- .num_pins = ARRAY_SIZE(gmii_3512_pins),
++ .name = "gmii_gmac0_grp",
++ .pins = gmii_gmac0_3512_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
++ },
++ {
++ .name = "gmii_gmac1_grp",
++ .pins = gmii_gmac1_3512_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
++ /* Bring out RGMII on the GMAC1 pins */
++ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "pcigrp",
+@@ -954,14 +971,15 @@ static const struct gemini_pin_group gem
+ .name = "gpio2agrp",
+ .pins = gpio2a_3512_pins,
+ .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
+- /* Conflict with GMII and extended parallel flash */
++ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ /* Conflict with GMII GMAC1 and extended parallel flash */
+ },
+ {
+ .name = "gpio2bgrp",
+ .pins = gpio2b_3512_pins,
+ .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
+- /* Conflict with GMII, extended parallel flash and LCD */
+- .mask = LCD_PADS_ENABLE,
++ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
++ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "gpio2cgrp",
+@@ -1441,9 +1459,12 @@ static const unsigned int usb_3516_pins[
+ };
+
+ /* GMII, ethernet pins */
+-static const unsigned int gmii_3516_pins[] = {
+- 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
+- 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
++static const unsigned int gmii_gmac0_3516_pins[] = {
++ 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
++};
++
++static const unsigned int gmii_gmac1_3516_pins[] = {
++ 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
+ };
+
+ static const unsigned int pci_3516_pins[] = {
+@@ -1585,10 +1606,10 @@ static const unsigned int gpio1c_3516_pi
+ /* The GPIO1D (28-31) pins overlap with TVC */
+ static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
+
+-/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
++/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
+ static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
+
+-/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
++/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
+ static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
+
+ /* The GPIO2C (8-31) pins overlap with PCI */
+@@ -1660,9 +1681,16 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(usb_3516_pins),
+ },
+ {
+- .name = "gmiigrp",
+- .pins = gmii_3516_pins,
+- .num_pins = ARRAY_SIZE(gmii_3516_pins),
++ .name = "gmii_gmac0_grp",
++ .pins = gmii_gmac0_3516_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
++ },
++ {
++ .name = "gmii_gmac1_grp",
++ .pins = gmii_gmac1_3516_pins,
++ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
++ /* Bring out RGMII on the GMAC1 pins */
++ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "pcigrp",
+@@ -1861,14 +1889,15 @@ static const struct gemini_pin_group gem
+ .name = "gpio2agrp",
+ .pins = gpio2a_3516_pins,
+ .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
+- /* Conflict with GMII and extended parallel flash */
++ .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ /* Conflict with GMII GMAC1 and extended parallel flash */
+ },
+ {
+ .name = "gpio2bgrp",
+ .pins = gpio2b_3516_pins,
+ .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
+- /* Conflict with GMII, extended parallel flash and LCD */
+- .mask = LCD_PADS_ENABLE,
++ /* Conflict with GMII GMAC1, extended parallel flash and LCD */
++ .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
+ },
+ {
+ .name = "gpio2cgrp",
+@@ -1971,7 +2000,7 @@ static const char * const icegrps[] = {
+ static const char * const idegrps[] = { "idegrp" };
+ static const char * const satagrps[] = { "satagrp" };
+ static const char * const usbgrps[] = { "usbgrp" };
+-static const char * const gmiigrps[] = { "gmiigrp" };
++static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
+ static const char * const pcigrps[] = { "pcigrp" };
+ static const char * const lpcgrps[] = { "lpcgrp" };
+ static const char * const lcdgrps[] = { "lcdgrp" };
diff --git a/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch b/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch
new file mode 100644
index 000000000000..2d7ed8304598
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch
@@ -0,0 +1,27 @@
+From 3f2941cb12a6d6a0ef4e53e0ecb8d2431d352964 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 13 Nov 2017 22:36:12 +0100
+Subject: [PATCH 08/31] pinctrl: gemini: Fix missing pad descriptions
+
+A pretty clever static checker found a bug in my patch: I added more
+bits to a bitmask but didn't extend the array indexed to the same
+bitmask.
+
+Fixes: 756a024f3983 ("pinctrl: gemini: Fix GMAC groups")
+Reported-by: Dan Carpenter <***@oracle.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -136,6 +136,8 @@ static const char * const gemini_padgrou
+ "PCI CLK",
+ NULL, NULL,
+ "TVC CLK",
++ NULL, NULL, NULL, NULL, NULL,
++ "GMAC1",
+ };
+
+ static const struct pinctrl_pin_desc gemini_3512_pins[] = {
diff --git a/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch b/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch
new file mode 100644
index 000000000000..46fc102c1d33
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch
@@ -0,0 +1,25 @@
+From c25653d045ce86c5ae472258fdaa39a6baaf75eb Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sun, 19 Nov 2017 10:57:27 +0100
+Subject: [PATCH 09/31] pinctrl: gemini: Add two missing GPIO groups
+
+The 3512 has two more GPIO groups on GPIO area 0, so let's
+make it possible to combine these with the function.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2015,7 +2015,8 @@ static const char * const sflashgrps[] =
+ static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
+ "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
+ "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
+- "gpio0jgrp", "gpio0kgrp" };
++ "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
++ "gpio0mgrp" };
+ static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
+ "gpio1dgrp" };
+ static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
diff --git a/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch b/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch
new file mode 100644
index 000000000000..1cab269a6493
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch
@@ -0,0 +1,25 @@
+From 88a5c6ad311588f178c5a88e4eeacc6d40b8ede3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Wed, 22 Nov 2017 21:04:14 +0100
+Subject: [PATCH 10/31] pinctrl: gemini: Fix usage of 3512 groups
+
+The pin config lookup function was still hardcoding the
+3516 pin set, which is obviously wrong. Use the pointer
+in the state container.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/pinctrl/pinctrl-gemini.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -2323,7 +2323,7 @@ static const struct gemini_pin_conf *gem
+ int i;
+
+ for (i = 0; i < pmx->nconfs; i++) {
+- retconf = &gemini_confs_3516[i];
++ retconf = &pmx->confs[i];
+ if (retconf->pin == pin)
+ return retconf;
+ }
diff --git a/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch b/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch
new file mode 100644
index 000000000000..5fefece493e3
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0011-pinctrl-gemini-Support-drive-strength-setting.patch
@@ -0,0 +1,198 @@
+From f147cf49ef39f5e87d5df9ef1fab52683bc75c63 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 2 Dec 2017 12:23:09 +0100
+Subject: [PATCH 11/31] pinctrl: gemini: Support drive strength setting
+
+The Gemini pin controller can set drive strength for a few
+select groups of pins (not individually). Implement this
+for GMAC0 and 1 (ethernet ports), IDE and PCI.
+
+Cc: ***@vger.kernel.org
+Reviewed-by: Rob Herring <***@kernel.org>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 3 +
+ drivers/pinctrl/pinctrl-gemini.c | 81 ++++++++++++++++++++++
+ 2 files changed, 84 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+@@ -17,6 +17,9 @@ and generic pin config nodes.
+
+ Supported configurations:
+ - skew-delay is supported on the Ethernet pins
++- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
++ entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
++ and "pcigrp".
+
+ Example:
+
+--- a/drivers/pinctrl/pinctrl-gemini.c
++++ b/drivers/pinctrl/pinctrl-gemini.c
+@@ -67,6 +67,9 @@ struct gemini_pmx {
+ * elements in .pins so we can iterate over that array
+ * @mask: bits to clear to enable this when doing pin muxing
+ * @value: bits to set to enable this when doing pin muxing
++ * @driving_mask: bitmask for the IO Pad driving register for this
++ * group, if it supports altering the driving strength of
++ * its lines.
+ */
+ struct gemini_pin_group {
+ const char *name;
+@@ -74,12 +77,14 @@ struct gemini_pin_group {
+ const unsigned int num_pins;
+ u32 mask;
+ u32 value;
++ u32 driving_mask;
+ };
+
+ /* Some straight-forward control registers */
+ #define GLOBAL_WORD_ID 0x00
+ #define GLOBAL_STATUS 0x04
+ #define GLOBAL_STATUS_FLPIN BIT(20)
++#define GLOBAL_IODRIVE 0x10
+ #define GLOBAL_GMAC_CTRL_SKEW 0x1c
+ #define GLOBAL_GMAC0_DATA_SKEW 0x20
+ #define GLOBAL_GMAC1_DATA_SKEW 0x24
+@@ -738,6 +743,7 @@ static const struct gemini_pin_group gem
+ /* Conflict with all flash usage */
+ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
+ PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
++ .driving_mask = GENMASK(21, 20),
+ },
+ {
+ .name = "satagrp",
+@@ -753,6 +759,7 @@ static const struct gemini_pin_group gem
+ .name = "gmii_gmac0_grp",
+ .pins = gmii_gmac0_3512_pins,
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
++ .driving_mask = GENMASK(17, 16),
+ },
+ {
+ .name = "gmii_gmac1_grp",
+@@ -760,6 +767,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
+ /* Bring out RGMII on the GMAC1 pins */
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ .driving_mask = GENMASK(19, 18),
+ },
+ {
+ .name = "pcigrp",
+@@ -767,6 +775,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(pci_3512_pins),
+ /* Conflict only with GPIO2 */
+ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
++ .driving_mask = GENMASK(23, 22),
+ },
+ {
+ .name = "lpcgrp",
+@@ -1671,6 +1680,7 @@ static const struct gemini_pin_group gem
+ /* Conflict with all flash usage */
+ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
+ PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
++ .driving_mask = GENMASK(21, 20),
+ },
+ {
+ .name = "satagrp",
+@@ -1686,6 +1696,7 @@ static const struct gemini_pin_group gem
+ .name = "gmii_gmac0_grp",
+ .pins = gmii_gmac0_3516_pins,
+ .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
++ .driving_mask = GENMASK(17, 16),
+ },
+ {
+ .name = "gmii_gmac1_grp",
+@@ -1693,6 +1704,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
+ /* Bring out RGMII on the GMAC1 pins */
+ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
++ .driving_mask = GENMASK(19, 18),
+ },
+ {
+ .name = "pcigrp",
+@@ -1700,6 +1712,7 @@ static const struct gemini_pin_group gem
+ .num_pins = ARRAY_SIZE(pci_3516_pins),
+ /* Conflict only with GPIO2 */
+ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
++ .driving_mask = GENMASK(23, 22),
+ },
+ {
+ .name = "lpcgrp",
+@@ -2394,9 +2407,77 @@ static int gemini_pinconf_set(struct pin
+ return ret;
+ }
+
++static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
++ unsigned selector,
++ unsigned long *configs,
++ unsigned num_configs)
++{
++ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
++ const struct gemini_pin_group *grp = NULL;
++ enum pin_config_param param;
++ u32 arg;
++ u32 val;
++ int i;
++
++ if (pmx->is_3512)
++ grp = &gemini_3512_pin_groups[selector];
++ if (pmx->is_3516)
++ grp = &gemini_3516_pin_groups[selector];
++
++ /* First figure out if this group supports configs */
++ if (!grp->driving_mask) {
++ dev_err(pmx->dev, "pin config group \"%s\" does "
++ "not support drive strength setting\n",
++ grp->name);
++ return -EINVAL;
++ }
++
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ arg = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_DRIVE_STRENGTH:
++ switch (arg) {
++ case 4:
++ val = 0;
++ break;
++ case 8:
++ val = 1;
++ break;
++ case 12:
++ val = 2;
++ break;
++ case 16:
++ val = 3;
++ break;
++ default:
++ dev_err(pmx->dev,
++ "invalid drive strength %d mA\n",
++ arg);
++ return -ENOTSUPP;
++ }
++ val <<= (ffs(grp->driving_mask) - 1);
++ regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
++ grp->driving_mask,
++ val);
++ dev_info(pmx->dev,
++ "set group %s to %d mA drive strength mask %08x val %08x\n",
++ grp->name, arg, grp->driving_mask, val);
++ break;
++ default:
++ dev_err(pmx->dev, "invalid config param %04x\n", param);
++ return -ENOTSUPP;
++ }
++ }
++
++ return 0;
++}
++
+ static const struct pinconf_ops gemini_pinconf_ops = {
+ .pin_config_get = gemini_pinconf_get,
+ .pin_config_set = gemini_pinconf_set,
++ .pin_config_group_set = gemini_pinconf_group_set,
+ .is_generic = true,
+ };
+
diff --git a/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch b/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch
new file mode 100644
index 000000000000..db701e3e9921
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch
@@ -0,0 +1,113 @@
+From f0674df220f3da81c173025636a904b395cf8f8b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sun, 19 Nov 2017 10:46:16 +0100
+Subject: [PATCH 12/31] ARM: dts: Add ethernet PHYs to the a bunch of Geminis
+
+These Gemini boards have Ethernet PHY on GPIO bit-banged
+MDIO, clearly defined in the corresponding OpenWRT
+ethernet patches since ages. Add them in accordance with
+the OpenWRT patch so we can use them when we add ethernet
+support.
+
+Reviewed-by: Andrew Lunn <***@lunn.ch>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/gemini-nas4220b.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-rut1xx.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-wbd111.dts | 13 +++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 18 ++++++++++++++++++
+ 4 files changed, 57 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -64,6 +64,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ ***@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-rut1xx.dts
++++ b/arch/arm/boot/dts/gemini-rut1xx.dts
+@@ -58,6 +58,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ ***@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -69,6 +69,19 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ ***@30000000 {
+ status = "okay";
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -69,6 +69,24 @@
+ };
+ };
+
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++
++ phy1: ethernet-***@3 {
++ reg = <3>;
++ device_type = "ethernet-phy";
++ };
++ };
++
+ soc {
+ ***@30000000 {
+ status = "okay";
diff --git a/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch b/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch
new file mode 100644
index 000000000000..cdf25a9258ee
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch
@@ -0,0 +1,272 @@
+From 2f08de94f207a4347053e1faa22c9a310c9c61b0 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 17 Nov 2017 16:36:32 +0100
+Subject: [PATCH 13/31] ARM: dts: Add basic devicetree for D-Link DNS-313
+
+This adds a basic device tree for the D-Link DNS-313
+NAS enclosure. This device has a thermal sensor and a
+fan so we add a thermal zone for the chassis in the
+device tree based on information from the product.
+
+Reviewed-by: Andrew Lunn <***@lunn.ch>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/gemini-dlink-dns-313.dts | 241 +++++++++++++++++++++++++++++
+ 2 files changed, 242 insertions(+)
+ create mode 100644 arch/arm/boot/dts/gemini-dlink-dns-313.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
+ exynos5800-peach-pi.dtb
+ dtb-$(CONFIG_ARCH_GEMINI) += \
+ gemini-dlink-dir-685.dtb \
++ gemini-dlink-dns-313.dtb \
+ gemini-nas4220b.dtb \
+ gemini-rut1xx.dtb \
+ gemini-sq201.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+@@ -0,0 +1,241 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
++ */
++
++/dts-v1/;
++
++#include "gemini.dtsi"
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++ model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
++ compatible = "dlink,dir-313", "cortina,gemini";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory {
++ /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ aliases {
++ mdio-gpio0 = &mdio0;
++ };
++
++ chosen {
++ stdout-path = "uart0:19200n8";
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ button-esc {
++ debounce_interval = <50>;
++ wakeup-source;
++ linux,code = <KEY_ESC>;
++ label = "reset";
++ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ led-power {
++ label = "dns313:blue:power";
++ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ led-disk-blue {
++ label = "dns313:blue:disk";
++ gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ };
++ led-disk-green {
++ label = "dns313:green:disk";
++ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ linux,default-trigger = "ide-disk";
++ /* Ideally should activate while reading */
++ };
++ led-disk-red {
++ label = "dns313:red:disk";
++ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ /* Ideally should activate while writing */
++ };
++ };
++
++ /*
++ * This is a ADDA AD0405GB-G73 fan @3000 and 6000 RPM.
++ */
++ fan0: gpio-fan {
++ compatible = "gpio-fan";
++ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
++ <&gpio0 12 GPIO_ACTIVE_HIGH>;
++ gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>;
++ cooling-min-level = <0>;
++ cooling-max-level = <2>;
++ #cooling-cells = <2>;
++ };
++
++
++ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
++ gpio-i2c {
++ compatible = "i2c-gpio";
++ sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ g751: temperature-***@48 {
++ compatible = "gmt,g751";
++ reg = <0x48>;
++ #thermal-sensor-cells = <0>;
++ };
++ };
++
++ thermal-zones {
++ chassis-thermal {
++ /* Poll every 20 seconds */
++ polling-delay = <20000>;
++ /* Poll every 2nd second when cooling */
++ polling-delay-passive = <2000>;
++
++ thermal-sensors = <&g751>;
++
++ /* Tripping points from the fan.script in the rootfs */
++ trips {
++ chassis_alert0: chassis-alert0 {
++ /* At 43 degrees turn on low speed */
++ temperature = <43000>;
++ hysteresis = <3000>;
++ type = "active";
++ };
++ chassis_alert1: chassis-alert1 {
++ /* At 47 degrees turn on high speed */
++ temperature = <47000>;
++ hysteresis = <3000>;
++ type = "active";
++ };
++ chassis_crit: chassis-crit {
++ /* Just shut down at 60 degrees */
++ temperature = <60000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&chassis_alert0>;
++ cooling-device = <&fan0 1 1>;
++ };
++ map1 {
++ trip = <&chassis_alert1>;
++ cooling-device = <&fan0 2 2>;
++ };
++ };
++ };
++ };
++
++ mdio0: ethernet-phy {
++ compatible = "virtual,mdio-gpio";
++ /* Uses MDC and MDIO */
++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
++ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* This is a Realtek RTL8211B Gigabit ethernet transceiver */
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ };
++
++ soc {
++ ***@30000000 {
++ status = "okay";
++ /* 512KB of flash */
++ reg = <0x30000000 0x00080000>;
++
++ /*
++ * This "RedBoot" is the Storlink derivative.
++ */
++ ***@0 {
++ label = "RedBoot";
++ reg = <0x00000000 0x00040000>;
++ read-only;
++ };
++ ***@40000 {
++ label = "MTD1";
++ reg = <0x00040000 0x00020000>;
++ read-only;
++ };
++ ***@60000 {
++ label = "MTD2";
++ reg = <0x00060000 0x00020000>;
++ read-only;
++ };
++ };
++
++ syscon: ***@40000000 {
++ pinctrl {
++ /*
++ */
++ gpio0_default_pins: pinctrl-gpio0 {
++ mux {
++ function = "gpio0";
++ groups =
++ /* Used by LEDs conflicts ICE */
++ "gpio0bgrp",
++ /* Used by ? conflicts ICE */
++ "gpio0cgrp",
++ /*
++ * Used by fan & G751, conflicts LPC,
++ * UART modem lines, SSP
++ */
++ "gpio0egrp",
++ /* Used by G751 */
++ "gpio0fgrp",
++ /* Used by MDIO */
++ "gpio0igrp";
++ };
++ };
++ gpio1_default_pins: pinctrl-gpio1 {
++ mux {
++ function = "gpio1";
++ /* Used by "reset" button */
++ groups = "gpio1dgrp";
++ };
++ };
++ };
++ };
++
++ sata: ***@46000000 {
++ /* The ROM uses this muxmode */
++ cortina,gemini-ata-muxmode = <3>;
++ cortina,gemini-enable-sata-bridge;
++ status = "okay";
++ };
++
++ gpio0: ***@4d000000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio0_default_pins>;
++ };
++
++ gpio1: ***@4e000000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gpio1_default_pins>;
++ };
++
++ ***@63000000 {
++ status = "okay";
++ };
++ };
++};
diff --git a/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch b/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch
new file mode 100644
index 000000000000..5cefd18aa94f
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch
@@ -0,0 +1,27 @@
+From eed839dc713fdb7b2579dbfea41d676386b8259b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sun, 10 Sep 2017 20:02:33 +0200
+Subject: [PATCH 14/31] ARM: dts: Flags D-Link DIR-685 I2C bus gpios
+
+These GPIOs are used in open drain mode, so make sure to
+flag them as such. Use the new separate scl/sda line
+GPIO bindings.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -99,8 +99,8 @@
+ gpio-i2c {
+ compatible = "i2c-gpio";
+ /* Collides with ICE */
+- gpios = <&gpio0 5 0>, /* SDA */
+- <&gpio0 6 0>; /* SCL */
++ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
diff --git a/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch b/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch
new file mode 100644
index 000000000000..429625ed2083
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch
@@ -0,0 +1,74 @@
+From dec551d2301f71a692ed1729a323c8259d36f849 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Wed, 11 Oct 2017 19:49:13 +0200
+Subject: [PATCH 15/31] ARM: dts: Add PCI to WBD111 and WBD222
+
+These two boards have mini-PCI card slots, so enable PCI
+on both of them.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/gemini-wbd111.dts | 22 ++++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 22 ++++++++++++++++++++++
+ 2 files changed, 44 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -138,5 +138,27 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
++
++ ***@50000000 {
++ status = "okay";
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
++ <0x4800 0 0 2 &pci_intc 1>,
++ <0x4800 0 0 3 &pci_intc 2>,
++ <0x4800 0 0 4 &pci_intc 3>,
++ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
++ <0x5000 0 0 2 &pci_intc 2>,
++ <0x5000 0 0 3 &pci_intc 3>,
++ <0x5000 0 0 4 &pci_intc 0>,
++ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
++ <0x5800 0 0 2 &pci_intc 3>,
++ <0x5800 0 0 3 &pci_intc 0>,
++ <0x5800 0 0 4 &pci_intc 1>,
++ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
++ <0x6000 0 0 2 &pci_intc 0>,
++ <0x6000 0 0 3 &pci_intc 1>,
++ <0x6000 0 0 4 &pci_intc 2>;
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -143,5 +143,27 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_default_pins>;
+ };
++
++ ***@50000000 {
++ status = "okay";
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
++ <0x4800 0 0 2 &pci_intc 1>,
++ <0x4800 0 0 3 &pci_intc 2>,
++ <0x4800 0 0 4 &pci_intc 3>,
++ <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
++ <0x5000 0 0 2 &pci_intc 2>,
++ <0x5000 0 0 3 &pci_intc 3>,
++ <0x5000 0 0 4 &pci_intc 0>,
++ <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
++ <0x5800 0 0 2 &pci_intc 3>,
++ <0x5800 0 0 3 &pci_intc 0>,
++ <0x5800 0 0 4 &pci_intc 1>,
++ <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
++ <0x6000 0 0 2 &pci_intc 0>,
++ <0x6000 0 0 3 &pci_intc 1>,
++ <0x6000 0 0 4 &pci_intc 2>;
++ };
+ };
+ };
diff --git a/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch b/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch
new file mode 100644
index 000000000000..e0cf267cccb9
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch
@@ -0,0 +1,113 @@
+From 9d3b968d13ba1eecaf22d5824cf8fd270c061534 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sat, 15 Jul 2017 21:02:06 +0200
+Subject: [PATCH 16/31] ARM: dts: Add TVE/TVC and ILI9322 panel to DIR-685
+
+This adds the TVE200/TVC TV-encoder and the Ilitek ILI9322 panel
+to the DIR-685 device tree.
+
+This brings graphics to this funky router and it is possible to
+even run a console on its tiny screen.
+
+Incidentally this requires us to disable the access to the
+parallel (NOR) flash, as the communication pins to the panel
+are shared with the flash memory.
+
+To access the flash, a separate kernel with the panel disabled
+and the flash enabled should be booted. The pin control selecting
+whether to use the lines cannot be altered at runtime due to
+hardware constraints.
+
+Cc: David Lechner <***@lechnology.com>
+Cc: Stefano Babic <***@denx.de>
+Cc: Ben Dooks <***@codethink.co.uk>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 63 +++++++++++++++++++++++++++++-
+ 1 file changed, 62 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -45,6 +45,47 @@
+ };
+ };
+
++ vdisp: regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "display-power";
++ regulator-min-microvolt = <3600000>;
++ regulator-max-microvolt = <3600000>;
++ /* Collides with LCD E */
++ gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ spi {
++ compatible = "spi-gpio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* Collides with IDE pins, that's cool (we do not use them) */
++ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
++ /* Collides with pflash CE1, not so cool */
++ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <1>;
++
++ panel: ***@0 {
++ compatible = "dlink,dir-685-panel", "ilitek,ili9322";
++ reg = <0>;
++ /* 50 ns min period = 20 MHz */
++ spi-max-frequency = <20000000>;
++ spi-cpol; /* Clock active low */
++ vcc-supply = <&vdisp>;
++ iovcc-supply = <&vdisp>;
++ vci-supply = <&vdisp>;
++
++ port {
++ panel_in: endpoint {
++ remote-endpoint = <&display_out>;
++ };
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ led-wps {
+@@ -115,7 +156,16 @@
+
+ soc {
+ ***@30000000 {
+- status = "okay";
++ /*
++ * Flash access is by default disabled, because it
++ * collides with the Chip Enable signal for the display
++ * panel, that reuse the parallel flash Chip Select 1
++ * (CS1). Enabling flash makes graphics stop working.
++ *
++ * We might be able to hack around this by letting
++ * GPIO poke around in the flash controller registers.
++ */
++ /* status = "okay"; */
+ /* 32MB of flash */
+ reg = <0x30000000 0x02000000>;
+
+@@ -242,5 +292,16 @@
+ ***@63000000 {
+ status = "okay";
+ };
++
++ display-***@6a000000 {
++ status = "okay";
++
++ ***@0 {
++ reg = <0>;
++ display_out: endpoint {
++ remote-endpoint = <&panel_in>;
++ };
++ };
++ };
+ };
+ };
diff --git a/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch b/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch
new file mode 100644
index 000000000000..3fe0b8f8ce45
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0017-watchdog-gemini-ftwdt010-rename-DT-bindings.patch
@@ -0,0 +1,88 @@
+From d73f6cc09bcbe258a72c06899215d1a3e8a7686d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:23 +0200
+Subject: [PATCH 17/31] watchdog: gemini/ftwdt010: rename DT bindings
+
+The device tree bindings are in two copies and also should be
+consolidated into a single Faraday Technology FTWDT010
+binding since we uncovered that this IP part is a standard
+IP from Faraday.
+
+Cc: ***@vger.kernel.org
+Acked-by: Rob Herring <***@kernel.org>
+Signed-off-by: Linus Walleij <***@linaro.org>
+Reviewed-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <***@iguana.be>
+---
+ .../bindings/watchdog/cortina,gemini-watchdog.txt | 17 -----------------
+ ...{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} | 11 ++++++++---
+ 2 files changed, 8 insertions(+), 20 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
+ rename Documentation/devicetree/bindings/watchdog/{cortina,gemin-watchdog.txt => faraday,ftwdt010.txt} (55%)
+
+--- a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
++++ /dev/null
+@@ -1,17 +0,0 @@
+-Cortina Systems Gemini SoC Watchdog
+-
+-Required properties:
+-- compatible : must be "cortina,gemini-watchdog"
+-- reg : shall contain base register location and length
+-- interrupts : shall contain the interrupt for the watchdog
+-
+-Optional properties:
+-- timeout-sec : the default watchdog timeout in seconds.
+-
+-Example:
+-
+-***@41000000 {
+- compatible = "cortina,gemini-watchdog";
+- reg = <0x41000000 0x1000>;
+- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+-};
+--- a/Documentation/devicetree/bindings/watchdog/cortina,gemin-watchdog.txt
++++ /dev/null
+@@ -1,17 +0,0 @@
+-Cortina Systems Gemini SoC Watchdog
+-
+-Required properties:
+-- compatible : must be "cortina,gemini-watchdog"
+-- reg : shall contain base register location and length
+-- interrupts : shall contain the interrupt for the watchdog
+-
+-Optional properties:
+-- timeout-sec : the default watchdog timeout in seconds.
+-
+-Example:
+-
+-***@41000000 {
+- compatible = "cortina,gemini-watchdog";
+- reg = <0x41000000 0x1000>;
+- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt
+@@ -0,0 +1,22 @@
++Faraday Technology FTWDT010 watchdog
++
++This is an IP part from Faraday Technology found in the Gemini
++SoCs and others.
++
++Required properties:
++- compatible : must be one of
++ "faraday,ftwdt010"
++ "cortina,gemini-watchdog", "faraday,ftwdt010"
++- reg : shall contain base register location and length
++- interrupts : shall contain the interrupt for the watchdog
++
++Optional properties:
++- timeout-sec : the default watchdog timeout in seconds.
++
++Example:
++
++***@41000000 {
++ compatible = "faraday,ftwdt010";
++ reg = <0x41000000 0x1000>;
++ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
++};
diff --git a/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch b/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch
new file mode 100644
index 000000000000..23c19893578d
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0018-watchdog-gemini-ftwdt010-rename-driver-and-symbols.patch
@@ -0,0 +1,527 @@
+From c197a5a04d658da490de08636066a6bdbebf16c5 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:24 +0200
+Subject: [PATCH 18/31] watchdog: gemini/ftwdt010: rename driver and symbols
+
+This renames all the driver files and symbols for the Gemini
+watchdog to FTWDT010 as it has been revealed that this IP block
+is a generic watchdog timer from Faraday Technology used in
+several SoC designs.
+
+Select this driver by default for the Gemini, it is a sensible
+driver to always have enabled.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+Reviewed-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <***@iguana.be>
+---
+ drivers/watchdog/Kconfig | 14 +--
+ drivers/watchdog/Makefile | 2 +-
+ drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} | 117 +++++++++++-----------
+ 3 files changed, 68 insertions(+), 65 deletions(-)
+ rename drivers/watchdog/{gemini_wdt.c => ftwdt010_wdt.c} (50%)
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -321,16 +321,18 @@ config 977_WATCHDOG
+
+ Not sure? It's safe to say N.
+
+-config GEMINI_WATCHDOG
+- tristate "Gemini watchdog"
+- depends on ARCH_GEMINI
++config FTWDT010_WATCHDOG
++ tristate "Faraday Technology FTWDT010 watchdog"
++ depends on ARM || COMPILE_TEST
+ select WATCHDOG_CORE
++ default ARCH_GEMINI
+ help
+- Say Y here if to include support for the watchdog timer
+- embedded in the Cortina Systems Gemini family of devices.
++ Say Y here if to include support for the Faraday Technology
++ FTWDT010 watchdog timer embedded in the Cortina Systems Gemini
++ family of devices.
+
+ To compile this driver as a module, choose M here: the
+- module will be called gemini_wdt.
++ module will be called ftwdt010_wdt.
+
+ config IXP4XX_WATCHDOG
+ tristate "IXP4xx Watchdog"
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -46,7 +46,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
+ obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
+ obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
+ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
+-obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
++obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+ obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
+ obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
+ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+--- a/drivers/watchdog/gemini_wdt.c
++++ /dev/null
+@@ -1,229 +0,0 @@
+-/*
+- * Watchdog driver for Cortina Systems Gemini SoC
+- *
+- * Copyright (C) 2017 Linus Walleij <***@linaro.org>
+- *
+- * Inspired by the out-of-tree drivers from OpenWRT:
+- * Copyright (C) 2009 Paulius Zaleckas <***@teltonika.lt>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/bitops.h>
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+-#include <linux/io.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/of_device.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-#include <linux/watchdog.h>
+-
+-#define GEMINI_WDCOUNTER 0x0
+-#define GEMINI_WDLOAD 0x4
+-#define GEMINI_WDRESTART 0x8
+-#define GEMINI_WDCR 0xC
+-
+-#define WDRESTART_MAGIC 0x5AB9
+-
+-#define WDCR_CLOCK_5MHZ BIT(4)
+-#define WDCR_SYS_RST BIT(1)
+-#define WDCR_ENABLE BIT(0)
+-
+-#define WDT_CLOCK 5000000 /* 5 MHz */
+-
+-struct gemini_wdt {
+- struct watchdog_device wdd;
+- struct device *dev;
+- void __iomem *base;
+-};
+-
+-static inline
+-struct gemini_wdt *to_gemini_wdt(struct watchdog_device *wdd)
+-{
+- return container_of(wdd, struct gemini_wdt, wdd);
+-}
+-
+-static int gemini_wdt_start(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(wdd->timeout * WDT_CLOCK, gwdt->base + GEMINI_WDLOAD);
+- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART);
+- /* set clock before enabling */
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
+- gwdt->base + GEMINI_WDCR);
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
+- gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_stop(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(0, gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_ping(struct watchdog_device *wdd)
+-{
+- struct gemini_wdt *gwdt = to_gemini_wdt(wdd);
+-
+- writel(WDRESTART_MAGIC, gwdt->base + GEMINI_WDRESTART);
+-
+- return 0;
+-}
+-
+-static int gemini_wdt_set_timeout(struct watchdog_device *wdd,
+- unsigned int timeout)
+-{
+- wdd->timeout = timeout;
+- if (watchdog_active(wdd))
+- gemini_wdt_start(wdd);
+-
+- return 0;
+-}
+-
+-static irqreturn_t gemini_wdt_interrupt(int irq, void *data)
+-{
+- struct gemini_wdt *gwdt = data;
+-
+- watchdog_notify_pretimeout(&gwdt->wdd);
+-
+- return IRQ_HANDLED;
+-}
+-
+-static const struct watchdog_ops gemini_wdt_ops = {
+- .start = gemini_wdt_start,
+- .stop = gemini_wdt_stop,
+- .ping = gemini_wdt_ping,
+- .set_timeout = gemini_wdt_set_timeout,
+- .owner = THIS_MODULE,
+-};
+-
+-static const struct watchdog_info gemini_wdt_info = {
+- .options = WDIOF_KEEPALIVEPING
+- | WDIOF_MAGICCLOSE
+- | WDIOF_SETTIMEOUT,
+- .identity = KBUILD_MODNAME,
+-};
+-
+-
+-static int gemini_wdt_probe(struct platform_device *pdev)
+-{
+- struct device *dev = &pdev->dev;
+- struct resource *res;
+- struct gemini_wdt *gwdt;
+- unsigned int reg;
+- int irq;
+- int ret;
+-
+- gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
+- if (!gwdt)
+- return -ENOMEM;
+-
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- gwdt->base = devm_ioremap_resource(dev, res);
+- if (IS_ERR(gwdt->base))
+- return PTR_ERR(gwdt->base);
+-
+- irq = platform_get_irq(pdev, 0);
+- if (!irq)
+- return -EINVAL;
+-
+- gwdt->dev = dev;
+- gwdt->wdd.info = &gemini_wdt_info;
+- gwdt->wdd.ops = &gemini_wdt_ops;
+- gwdt->wdd.min_timeout = 1;
+- gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
+- gwdt->wdd.parent = dev;
+-
+- /*
+- * If 'timeout-sec' unspecified in devicetree, assume a 13 second
+- * default.
+- */
+- gwdt->wdd.timeout = 13U;
+- watchdog_init_timeout(&gwdt->wdd, 0, dev);
+-
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- if (reg & WDCR_ENABLE) {
+- /* Watchdog was enabled by the bootloader, disable it. */
+- reg &= ~WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+- }
+-
+- ret = devm_request_irq(dev, irq, gemini_wdt_interrupt, 0,
+- "watchdog bark", gwdt);
+- if (ret)
+- return ret;
+-
+- ret = devm_watchdog_register_device(dev, &gwdt->wdd);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to register watchdog\n");
+- return ret;
+- }
+-
+- /* Set up platform driver data */
+- platform_set_drvdata(pdev, gwdt);
+- dev_info(dev, "Gemini watchdog driver enabled\n");
+-
+- return 0;
+-}
+-
+-static int __maybe_unused gemini_wdt_suspend(struct device *dev)
+-{
+- struct gemini_wdt *gwdt = dev_get_drvdata(dev);
+- unsigned int reg;
+-
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- reg &= ~WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+-
+- return 0;
+-}
+-
+-static int __maybe_unused gemini_wdt_resume(struct device *dev)
+-{
+- struct gemini_wdt *gwdt = dev_get_drvdata(dev);
+- unsigned int reg;
+-
+- if (watchdog_active(&gwdt->wdd)) {
+- reg = readw(gwdt->base + GEMINI_WDCR);
+- reg |= WDCR_ENABLE;
+- writel(reg, gwdt->base + GEMINI_WDCR);
+- }
+-
+- return 0;
+-}
+-
+-static const struct dev_pm_ops gemini_wdt_dev_pm_ops = {
+- SET_SYSTEM_SLEEP_PM_OPS(gemini_wdt_suspend,
+- gemini_wdt_resume)
+-};
+-
+-#ifdef CONFIG_OF
+-static const struct of_device_id gemini_wdt_match[] = {
+- { .compatible = "cortina,gemini-watchdog" },
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, gemini_wdt_match);
+-#endif
+-
+-static struct platform_driver gemini_wdt_driver = {
+- .probe = gemini_wdt_probe,
+- .driver = {
+- .name = "gemini-wdt",
+- .of_match_table = of_match_ptr(gemini_wdt_match),
+- .pm = &gemini_wdt_dev_pm_ops,
+- },
+-};
+-module_platform_driver(gemini_wdt_driver);
+-MODULE_AUTHOR("Linus Walleij");
+-MODULE_DESCRIPTION("Watchdog driver for Gemini");
+-MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/watchdog/ftwdt010_wdt.c
+@@ -0,0 +1,230 @@
++/*
++ * Watchdog driver for Faraday Technology FTWDT010
++ *
++ * Copyright (C) 2017 Linus Walleij <***@linaro.org>
++ *
++ * Inspired by the out-of-tree drivers from OpenWRT:
++ * Copyright (C) 2009 Paulius Zaleckas <***@teltonika.lt>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/bitops.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/watchdog.h>
++
++#define FTWDT010_WDCOUNTER 0x0
++#define FTWDT010_WDLOAD 0x4
++#define FTWDT010_WDRESTART 0x8
++#define FTWDT010_WDCR 0xC
++
++#define WDRESTART_MAGIC 0x5AB9
++
++#define WDCR_CLOCK_5MHZ BIT(4)
++#define WDCR_SYS_RST BIT(1)
++#define WDCR_ENABLE BIT(0)
++
++#define WDT_CLOCK 5000000 /* 5 MHz */
++
++struct ftwdt010_wdt {
++ struct watchdog_device wdd;
++ struct device *dev;
++ void __iomem *base;
++};
++
++static inline
++struct ftwdt010_wdt *to_ftwdt010_wdt(struct watchdog_device *wdd)
++{
++ return container_of(wdd, struct ftwdt010_wdt, wdd);
++}
++
++static int ftwdt010_wdt_start(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
++ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
++ /* set clock before enabling */
++ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
++ gwdt->base + FTWDT010_WDCR);
++ writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
++ gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_stop(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(0, gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_ping(struct watchdog_device *wdd)
++{
++ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++
++ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
++
++ return 0;
++}
++
++static int ftwdt010_wdt_set_timeout(struct watchdog_device *wdd,
++ unsigned int timeout)
++{
++ wdd->timeout = timeout;
++ if (watchdog_active(wdd))
++ ftwdt010_wdt_start(wdd);
++
++ return 0;
++}
++
++static irqreturn_t ftwdt010_wdt_interrupt(int irq, void *data)
++{
++ struct ftwdt010_wdt *gwdt = data;
++
++ watchdog_notify_pretimeout(&gwdt->wdd);
++
++ return IRQ_HANDLED;
++}
++
++static const struct watchdog_ops ftwdt010_wdt_ops = {
++ .start = ftwdt010_wdt_start,
++ .stop = ftwdt010_wdt_stop,
++ .ping = ftwdt010_wdt_ping,
++ .set_timeout = ftwdt010_wdt_set_timeout,
++ .owner = THIS_MODULE,
++};
++
++static const struct watchdog_info ftwdt010_wdt_info = {
++ .options = WDIOF_KEEPALIVEPING
++ | WDIOF_MAGICCLOSE
++ | WDIOF_SETTIMEOUT,
++ .identity = KBUILD_MODNAME,
++};
++
++
++static int ftwdt010_wdt_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ struct ftwdt010_wdt *gwdt;
++ unsigned int reg;
++ int irq;
++ int ret;
++
++ gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
++ if (!gwdt)
++ return -ENOMEM;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ gwdt->base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(gwdt->base))
++ return PTR_ERR(gwdt->base);
++
++ irq = platform_get_irq(pdev, 0);
++ if (!irq)
++ return -EINVAL;
++
++ gwdt->dev = dev;
++ gwdt->wdd.info = &ftwdt010_wdt_info;
++ gwdt->wdd.ops = &ftwdt010_wdt_ops;
++ gwdt->wdd.min_timeout = 1;
++ gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
++ gwdt->wdd.parent = dev;
++
++ /*
++ * If 'timeout-sec' unspecified in devicetree, assume a 13 second
++ * default.
++ */
++ gwdt->wdd.timeout = 13U;
++ watchdog_init_timeout(&gwdt->wdd, 0, dev);
++
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ if (reg & WDCR_ENABLE) {
++ /* Watchdog was enabled by the bootloader, disable it. */
++ reg &= ~WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++ }
++
++ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
++ "watchdog bark", gwdt);
++ if (ret)
++ return ret;
++
++ ret = devm_watchdog_register_device(dev, &gwdt->wdd);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register watchdog\n");
++ return ret;
++ }
++
++ /* Set up platform driver data */
++ platform_set_drvdata(pdev, gwdt);
++ dev_info(dev, "FTWDT010 watchdog driver enabled\n");
++
++ return 0;
++}
++
++static int __maybe_unused ftwdt010_wdt_suspend(struct device *dev)
++{
++ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
++ unsigned int reg;
++
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ reg &= ~WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++
++ return 0;
++}
++
++static int __maybe_unused ftwdt010_wdt_resume(struct device *dev)
++{
++ struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
++ unsigned int reg;
++
++ if (watchdog_active(&gwdt->wdd)) {
++ reg = readw(gwdt->base + FTWDT010_WDCR);
++ reg |= WDCR_ENABLE;
++ writel(reg, gwdt->base + FTWDT010_WDCR);
++ }
++
++ return 0;
++}
++
++static const struct dev_pm_ops ftwdt010_wdt_dev_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ftwdt010_wdt_suspend,
++ ftwdt010_wdt_resume)
++};
++
++#ifdef CONFIG_OF
++static const struct of_device_id ftwdt010_wdt_match[] = {
++ { .compatible = "faraday,ftwdt010" },
++ { .compatible = "cortina,gemini-watchdog" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ftwdt010_wdt_match);
++#endif
++
++static struct platform_driver ftwdt010_wdt_driver = {
++ .probe = ftwdt010_wdt_probe,
++ .driver = {
++ .name = "ftwdt010-wdt",
++ .of_match_table = of_match_ptr(ftwdt010_wdt_match),
++ .pm = &ftwdt010_wdt_dev_pm_ops,
++ },
++};
++module_platform_driver(ftwdt010_wdt_driver);
++MODULE_AUTHOR("Linus Walleij");
++MODULE_DESCRIPTION("Watchdog driver for Faraday Technology FTWDT010");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch b/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch
new file mode 100644
index 000000000000..23c4ab5c0d67
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch
@@ -0,0 +1,93 @@
+From 4347a0b0699989b889857c9d4ccfbce339859f13 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 16 Oct 2017 22:54:25 +0200
+Subject: [PATCH 19/31] watchdog: ftwdt010: Make interrupt optional
+
+The Moxart does not appear to be using the interrupt from the
+watchdog timer, maybe it's not even routed, so as to support
+more architectures with this driver, make the interrupt
+optional.
+
+While we are at it: actually enable the use of the interrupt
+if present by setting the right bit in the control register
+and define the missing control register bits.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+Reviewed-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Guenter Roeck <***@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <***@iguana.be>
+---
+ drivers/watchdog/ftwdt010_wdt.c | 30 ++++++++++++++++++------------
+ 1 file changed, 18 insertions(+), 12 deletions(-)
+
+--- a/drivers/watchdog/ftwdt010_wdt.c
++++ b/drivers/watchdog/ftwdt010_wdt.c
+@@ -30,6 +30,8 @@
+ #define WDRESTART_MAGIC 0x5AB9
+
+ #define WDCR_CLOCK_5MHZ BIT(4)
++#define WDCR_WDEXT BIT(3)
++#define WDCR_WDINTR BIT(2)
+ #define WDCR_SYS_RST BIT(1)
+ #define WDCR_ENABLE BIT(0)
+
+@@ -39,6 +41,7 @@ struct ftwdt010_wdt {
+ struct watchdog_device wdd;
+ struct device *dev;
+ void __iomem *base;
++ bool has_irq;
+ };
+
+ static inline
+@@ -50,14 +53,17 @@ struct ftwdt010_wdt *to_ftwdt010_wdt(str
+ static int ftwdt010_wdt_start(struct watchdog_device *wdd)
+ {
+ struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
++ u32 enable;
+
+ writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
+ writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
+ /* set clock before enabling */
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
+- gwdt->base + FTWDT010_WDCR);
+- writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
+- gwdt->base + FTWDT010_WDCR);
++ enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST;
++ writel(enable, gwdt->base + FTWDT010_WDCR);
++ if (gwdt->has_irq)
++ enable |= WDCR_WDINTR;
++ enable |= WDCR_ENABLE;
++ writel(enable, gwdt->base + FTWDT010_WDCR);
+
+ return 0;
+ }
+@@ -133,10 +139,6 @@ static int ftwdt010_wdt_probe(struct pla
+ if (IS_ERR(gwdt->base))
+ return PTR_ERR(gwdt->base);
+
+- irq = platform_get_irq(pdev, 0);
+- if (!irq)
+- return -EINVAL;
+-
+ gwdt->dev = dev;
+ gwdt->wdd.info = &ftwdt010_wdt_info;
+ gwdt->wdd.ops = &ftwdt010_wdt_ops;
+@@ -158,10 +160,14 @@ static int ftwdt010_wdt_probe(struct pla
+ writel(reg, gwdt->base + FTWDT010_WDCR);
+ }
+
+- ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
+- "watchdog bark", gwdt);
+- if (ret)
+- return ret;
++ irq = platform_get_irq(pdev, 0);
++ if (irq) {
++ ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
++ "watchdog bark", gwdt);
++ if (ret)
++ return ret;
++ gwdt->has_irq = true;
++ }
+
+ ret = devm_watchdog_register_device(dev, &gwdt->wdd);
+ if (ret) {
diff --git a/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch b/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch
new file mode 100644
index 000000000000..f1bbe0a15ff5
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0020-soc-Add-SoC-driver-for-Gemini.patch
@@ -0,0 +1,113 @@
+From b0a88a861b036124ef2d6acfe6dd87cfde63e750 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 22 Dec 2017 00:19:08 +0100
+Subject: [PATCH 20/31] soc: Add SoC driver for Gemini
+
+This adds an SoC driver for the Gemini. Currently there
+is only one thing not fitting into any other framework,
+and that is the bus arbitration setting.
+
+All Gemini vendor trees seem to be setting this register to
+exactly the same arbitration so we just add a small code
+snippet to do this at subsys_init() time before any other
+drivers kick in.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+Signed-off-by: Arnd Bergmann <***@arndb.de>
+---
+ drivers/soc/Makefile | 1 +
+ drivers/soc/gemini/Makefile | 2 ++
+ drivers/soc/gemini/soc-gemini.c | 71 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+)
+ create mode 100644 drivers/soc/gemini/Makefile
+ create mode 100644 drivers/soc/gemini/soc-gemini.c
+
+--- a/drivers/soc/Makefile
++++ b/drivers/soc/Makefile
+@@ -9,6 +9,7 @@ obj-y += bcm/
+ obj-$(CONFIG_ARCH_DOVE) += dove/
+ obj-$(CONFIG_MACH_DOVE) += dove/
+ obj-y += fsl/
++obj-$(CONFIG_ARCH_GEMINI) += gemini/
+ obj-$(CONFIG_ARCH_MXC) += imx/
+ obj-$(CONFIG_SOC_XWAY) += lantiq/
+ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+--- /dev/null
++++ b/drivers/soc/gemini/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-y += soc-gemini.o
+--- /dev/null
++++ b/drivers/soc/gemini/soc-gemini.c
+@@ -0,0 +1,71 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2017 Linaro Ltd.
++ *
++ * Author: Linus Walleij <***@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2, as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
++#include <linux/of.h>
++
++#define GLOBAL_WORD_ID 0x00
++#define GEMINI_GLOBAL_ARB1_CTRL 0x2c
++#define GEMINI_ARB1_BURST_MASK GENMASK(21, 16)
++#define GEMINI_ARB1_BURST_SHIFT 16
++/* These all define the priority on the BUS2 backplane */
++#define GEMINI_ARB1_PRIO_MASK GENMASK(9, 0)
++#define GEMINI_ARB1_DMAC_HIGH_PRIO BIT(0)
++#define GEMINI_ARB1_IDE_HIGH_PRIO BIT(1)
++#define GEMINI_ARB1_RAID_HIGH_PRIO BIT(2)
++#define GEMINI_ARB1_SECURITY_HIGH_PRIO BIT(3)
++#define GEMINI_ARB1_GMAC0_HIGH_PRIO BIT(4)
++#define GEMINI_ARB1_GMAC1_HIGH_PRIO BIT(5)
++#define GEMINI_ARB1_USB0_HIGH_PRIO BIT(6)
++#define GEMINI_ARB1_USB1_HIGH_PRIO BIT(7)
++#define GEMINI_ARB1_PCI_HIGH_PRIO BIT(8)
++#define GEMINI_ARB1_TVE_HIGH_PRIO BIT(9)
++
++#define GEMINI_DEFAULT_BURST_SIZE 0x20
++#define GEMINI_DEFAULT_PRIO (GEMINI_ARB1_GMAC0_HIGH_PRIO | \
++ GEMINI_ARB1_GMAC1_HIGH_PRIO)
++
++static int __init gemini_soc_init(void)
++{
++ struct regmap *map;
++ u32 rev;
++ u32 val;
++ int ret;
++
++ /* Multiplatform guard, only proceed on Gemini */
++ if (!of_machine_is_compatible("cortina,gemini"))
++ return 0;
++
++ map = syscon_regmap_lookup_by_compatible("cortina,gemini-syscon");
++ if (IS_ERR(map))
++ return PTR_ERR(map);
++ ret = regmap_read(map, GLOBAL_WORD_ID, &rev);
++ if (ret)
++ return ret;
++
++ val = (GEMINI_DEFAULT_BURST_SIZE << GEMINI_ARB1_BURST_SHIFT) |
++ GEMINI_DEFAULT_PRIO;
++
++ /* Set up system arbitration */
++ regmap_update_bits(map,
++ GEMINI_GLOBAL_ARB1_CTRL,
++ GEMINI_ARB1_BURST_MASK | GEMINI_ARB1_PRIO_MASK,
++ val);
++
++ pr_info("Gemini SoC %04x revision %02x, set arbitration %08x\n",
++ rev >> 8, rev & 0xff, val);
++
++ return 0;
++}
++subsys_initcall(gemini_soc_init);
diff --git a/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch b/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch
new file mode 100644
index 000000000000..19653d5ad1ae
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch
@@ -0,0 +1,119 @@
+From 49bc597009f52ec8970269f6201d3ed415a844ee Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 12 Jan 2018 22:34:23 +0100
+Subject: [PATCH 21/31] net: ethernet: Add DT bindings for the Gemini ethernet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds the device tree bindings for the Gemini ethernet
+controller. It is pretty straight-forward, using standard
+bindings and modelling the two child ports as child devices
+under the parent ethernet controller device.
+
+Cc: ***@vger.kernel.org
+Cc: Tobias Waldvogel <***@gmail.com>
+Cc: Michał Mirosław <mirq-***@rere.qmqm.pl>
+Reviewed-by: Rob Herring <***@kernel.org>
+Signed-off-by: Linus Walleij <***@linaro.org>
+Signed-off-by: David S. Miller <***@davemloft.net>
+---
+ .../bindings/net/cortina,gemini-ethernet.txt | 92 ++++++++++++++++++++++
+ 1 file changed, 92 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+@@ -0,0 +1,92 @@
++Cortina Systems Gemini Ethernet Controller
++==========================================
++
++This ethernet controller is found in the Gemini SoC family:
++StorLink SL3512 and SL3516, also known as Cortina Systems
++CS3512 and CS3516.
++
++Required properties:
++- compatible: must be "cortina,gemini-ethernet"
++- reg: must contain the global registers and the V-bit and A-bit
++ memory areas, in total three register sets.
++- syscon: a phandle to the system controller
++- #address-cells: must be specified, must be <1>
++- #size-cells: must be specified, must be <1>
++- ranges: should be state like this giving a 1:1 address translation
++ for the subnodes
++
++The subnodes represents the two ethernet ports in this device.
++They are not independent of each other since they share resources
++in the parent node, and are thus children.
++
++Required subnodes:
++- port0: contains the resources for ethernet port 0
++- port1: contains the resources for ethernet port 1
++
++Required subnode properties:
++- compatible: must be "cortina,gemini-ethernet-port"
++- reg: must contain two register areas: the DMA/TOE memory and
++ the GMAC memory area of the port
++- interrupts: should contain the interrupt line of the port.
++ this is nominally a level interrupt active high.
++- resets: this must provide an SoC-integrated reset line for
++ the port.
++- clocks: this should contain a handle to the PCLK clock for
++ clocking the silicon in this port
++- clock-names: must be "PCLK"
++
++Optional subnode properties:
++- phy-mode: see ethernet.txt
++- phy-handle: see ethernet.txt
++
++Example:
++
++mdio-bus {
++ (...)
++ phy0: ethernet-***@1 {
++ reg = <1>;
++ device_type = "ethernet-phy";
++ };
++ phy1: ethernet-***@3 {
++ reg = <3>;
++ device_type = "ethernet-phy";
++ };
++};
++
++
++***@60000000 {
++ compatible = "cortina,gemini-ethernet";
++ reg = <0x60000000 0x4000>, /* Global registers, queue */
++ <0x60004000 0x2000>, /* V-bit */
++ <0x60006000 0x2000>; /* A-bit */
++ syscon = <&syscon>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ gmac0: ethernet-***@0 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
++ <0x6000a000 0x2000>; /* Port 0 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC0>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
++ clock-names = "PCLK";
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++
++ gmac1: ethernet-***@1 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
++ <0x6000e000 0x2000>; /* Port 1 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC1>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
++ clock-names = "PCLK";
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++};
diff --git a/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch b/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch
new file mode 100644
index 000000000000..bad9bfa34e4c
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch
@@ -0,0 +1,3661 @@
+From 07826b86d4ce4d35fd1674d7f78e4b2060ab2910 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 12 Jan 2018 22:34:24 +0100
+Subject: [PATCH 22/31] net: ethernet: Add a driver for Gemini gigabit ethernet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Gemini ethernet has been around for years as an out-of-tree
+patch used with the NAS boxen and routers built on StorLink
+SL3512 and SL3516, later Storm Semiconductor, later Cortina
+Systems. These ASICs are still being deployed and brand new
+off-the-shelf systems using it can easily be acquired.
+
+The full name of the IP block is "Net Engine and Gigabit
+Ethernet MAC" commonly just called "GMAC".
+
+The hardware block contains a common TCP Offload Enginer (TOE)
+that can be used by both MACs. The current driver does not use
+it.
+
+Cc: Tobias Waldvogel <***@gmail.com>
+Signed-off-by: Michał Mirosław <mirq-***@rere.qmqm.pl>
+Signed-off-by: Linus Walleij <***@linaro.org>
+Signed-off-by: David S. Miller <***@davemloft.net>
+---
+ MAINTAINERS | 2 +
+ drivers/net/ethernet/Kconfig | 1 +
+ drivers/net/ethernet/Makefile | 1 +
+ drivers/net/ethernet/cortina/Kconfig | 22 +
+ drivers/net/ethernet/cortina/Makefile | 4 +
+ drivers/net/ethernet/cortina/gemini.c | 2593 +++++++++++++++++++++++++++++++++
+ drivers/net/ethernet/cortina/gemini.h | 958 ++++++++++++
+ 7 files changed, 3581 insertions(+)
+ create mode 100644 drivers/net/ethernet/cortina/Kconfig
+ create mode 100644 drivers/net/ethernet/cortina/Makefile
+ create mode 100644 drivers/net/ethernet/cortina/gemini.c
+ create mode 100644 drivers/net/ethernet/cortina/gemini.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1327,8 +1327,10 @@ T: git git://github.com/ulli-kroll/linux
+ S: Maintained
+ F: Documentation/devicetree/bindings/arm/gemini.txt
+ F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
++F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+ F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
+ F: arch/arm/mach-gemini/
++F: drivers/net/ethernet/cortina/gemini/*
+ F: drivers/pinctrl/pinctrl-gemini.c
+ F: drivers/rtc/rtc-ftrtc010.c
+
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -42,6 +42,7 @@ source "drivers/net/ethernet/cavium/Kcon
+ source "drivers/net/ethernet/chelsio/Kconfig"
+ source "drivers/net/ethernet/cirrus/Kconfig"
+ source "drivers/net/ethernet/cisco/Kconfig"
++source "drivers/net/ethernet/cortina/Kconfig"
+
+ config CX_ECAT
+ tristate "Beckhoff CX5020 EtherCAT master support"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_VENDOR_CAVIUM) += caviu
+ obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
+ obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
+ obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
++obj-$(CONFIG_NET_VENDOR_CORTINA) += cortina/
+ obj-$(CONFIG_CX_ECAT) += ec_bhf.o
+ obj-$(CONFIG_DM9000) += davicom/
+ obj-$(CONFIG_DNET) += dnet.o
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/Kconfig
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0
++# Cortina ethernet devices
++
++config NET_VENDOR_CORTINA
++ bool "Cortina Gemini devices"
++ default y
++ ---help---
++ If you have a network (Ethernet) card belonging to this class, say Y
++ and read the Ethernet-HOWTO, available from
++ <http://www.tldp.org/docs.html#howto>.
++
++if NET_VENDOR_CORTINA
++
++config GEMINI_ETHERNET
++ tristate "Gemini Gigabit Ethernet support"
++ depends on OF
++ select PHYLIB
++ select CRC32
++ ---help---
++ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
++
++endif # NET_VENDOR_CORTINA
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++# Makefile for the Cortina Gemini network device drivers.
++
++obj-$(CONFIG_GEMINI_ETHERNET) += gemini.o
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -0,0 +1,2593 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Ethernet device driver for Cortina Systems Gemini SoC
++ * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
++ * Net Engine and Gigabit Ethernet MAC (GMAC)
++ * This hardware contains a TCP Offload Engine (TOE) but currently the
++ * driver does not make use of it.
++ *
++ * Authors:
++ * Linus Walleij <***@linaro.org>
++ * Tobias Waldvogel <***@gmail.com> (OpenWRT)
++ * Michał Mirosław <mirq-***@rere.qmqm.pl>
++ * Paulius Zaleckas <***@gmail.com>
++ * Giuseppe De Robertis <***@ba.infn.it>
++ * Gary Chen & Ch Hsu Storlink Semiconductor
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++#include <linux/cache.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/of_mdio.h>
++#include <linux/of_net.h>
++#include <linux/of_platform.h>
++#include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
++#include <linux/skbuff.h>
++#include <linux/phy.h>
++#include <linux/crc32.h>
++#include <linux/ethtool.h>
++#include <linux/tcp.h>
++#include <linux/u64_stats_sync.h>
++
++#include <linux/in.h>
++#include <linux/ip.h>
++#include <linux/ipv6.h>
++
++#include "gemini.h"
++
++#define DRV_NAME "gmac-gemini"
++#define DRV_VERSION "1.0"
++
++#define HSIZE_8 0x00
++#define HSIZE_16 0x01
++#define HSIZE_32 0x02
++
++#define HBURST_SINGLE 0x00
++#define HBURST_INCR 0x01
++#define HBURST_INCR4 0x02
++#define HBURST_INCR8 0x03
++
++#define HPROT_DATA_CACHE BIT(0)
++#define HPROT_PRIVILIGED BIT(1)
++#define HPROT_BUFFERABLE BIT(2)
++#define HPROT_CACHABLE BIT(3)
++
++#define DEFAULT_RX_COALESCE_NSECS 0
++#define DEFAULT_GMAC_RXQ_ORDER 9
++#define DEFAULT_GMAC_TXQ_ORDER 8
++#define DEFAULT_RX_BUF_ORDER 11
++#define DEFAULT_NAPI_WEIGHT 64
++#define TX_MAX_FRAGS 16
++#define TX_QUEUE_NUM 1 /* max: 6 */
++#define RX_MAX_ALLOC_ORDER 2
++
++#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
++ GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
++#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
++ GMAC0_SWTQ00_FIN_INT_BIT)
++#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
++
++#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
++
++/**
++ * struct gmac_queue_page - page buffer per-page info
++ */
++struct gmac_queue_page {
++ struct page *page;
++ dma_addr_t mapping;
++};
++
++struct gmac_txq {
++ struct gmac_txdesc *ring;
++ struct sk_buff **skb;
++ unsigned int cptr;
++ unsigned int noirq_packets;
++};
++
++struct gemini_ethernet;
++
++struct gemini_ethernet_port {
++ u8 id; /* 0 or 1 */
++
++ struct gemini_ethernet *geth;
++ struct net_device *netdev;
++ struct device *dev;
++ void __iomem *dma_base;
++ void __iomem *gmac_base;
++ struct clk *pclk;
++ struct reset_control *reset;
++ int irq;
++ __le32 mac_addr[3];
++
++ void __iomem *rxq_rwptr;
++ struct gmac_rxdesc *rxq_ring;
++ unsigned int rxq_order;
++
++ struct napi_struct napi;
++ struct hrtimer rx_coalesce_timer;
++ unsigned int rx_coalesce_nsecs;
++ unsigned int freeq_refill;
++ struct gmac_txq txq[TX_QUEUE_NUM];
++ unsigned int txq_order;
++ unsigned int irq_every_tx_packets;
++
++ dma_addr_t rxq_dma_base;
++ dma_addr_t txq_dma_base;
++
++ unsigned int msg_enable;
++ spinlock_t config_lock; /* Locks config register */
++
++ struct u64_stats_sync tx_stats_syncp;
++ struct u64_stats_sync rx_stats_syncp;
++ struct u64_stats_sync ir_stats_syncp;
++
++ struct rtnl_link_stats64 stats;
++ u64 hw_stats[RX_STATS_NUM];
++ u64 rx_stats[RX_STATUS_NUM];
++ u64 rx_csum_stats[RX_CHKSUM_NUM];
++ u64 rx_napi_exits;
++ u64 tx_frag_stats[TX_MAX_FRAGS];
++ u64 tx_frags_linearized;
++ u64 tx_hw_csummed;
++};
++
++struct gemini_ethernet {
++ struct device *dev;
++ void __iomem *base;
++ struct gemini_ethernet_port *port0;
++ struct gemini_ethernet_port *port1;
++
++ spinlock_t irq_lock; /* Locks IRQ-related registers */
++ unsigned int freeq_order;
++ unsigned int freeq_frag_order;
++ struct gmac_rxdesc *freeq_ring;
++ dma_addr_t freeq_dma_base;
++ struct gmac_queue_page *freeq_pages;
++ unsigned int num_freeq_pages;
++ spinlock_t freeq_lock; /* Locks queue from reentrance */
++};
++
++#define GMAC_STATS_NUM ( \
++ RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
++ TX_MAX_FRAGS + 2)
++
++static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
++ "GMAC_IN_DISCARDS",
++ "GMAC_IN_ERRORS",
++ "GMAC_IN_MCAST",
++ "GMAC_IN_BCAST",
++ "GMAC_IN_MAC1",
++ "GMAC_IN_MAC2",
++ "RX_STATUS_GOOD_FRAME",
++ "RX_STATUS_TOO_LONG_GOOD_CRC",
++ "RX_STATUS_RUNT_FRAME",
++ "RX_STATUS_SFD_NOT_FOUND",
++ "RX_STATUS_CRC_ERROR",
++ "RX_STATUS_TOO_LONG_BAD_CRC",
++ "RX_STATUS_ALIGNMENT_ERROR",
++ "RX_STATUS_TOO_LONG_BAD_ALIGN",
++ "RX_STATUS_RX_ERR",
++ "RX_STATUS_DA_FILTERED",
++ "RX_STATUS_BUFFER_FULL",
++ "RX_STATUS_11",
++ "RX_STATUS_12",
++ "RX_STATUS_13",
++ "RX_STATUS_14",
++ "RX_STATUS_15",
++ "RX_CHKSUM_IP_UDP_TCP_OK",
++ "RX_CHKSUM_IP_OK_ONLY",
++ "RX_CHKSUM_NONE",
++ "RX_CHKSUM_3",
++ "RX_CHKSUM_IP_ERR_UNKNOWN",
++ "RX_CHKSUM_IP_ERR",
++ "RX_CHKSUM_TCP_UDP_ERR",
++ "RX_CHKSUM_7",
++ "RX_NAPI_EXITS",
++ "TX_FRAGS[1]",
++ "TX_FRAGS[2]",
++ "TX_FRAGS[3]",
++ "TX_FRAGS[4]",
++ "TX_FRAGS[5]",
++ "TX_FRAGS[6]",
++ "TX_FRAGS[7]",
++ "TX_FRAGS[8]",
++ "TX_FRAGS[9]",
++ "TX_FRAGS[10]",
++ "TX_FRAGS[11]",
++ "TX_FRAGS[12]",
++ "TX_FRAGS[13]",
++ "TX_FRAGS[14]",
++ "TX_FRAGS[15]",
++ "TX_FRAGS[16+]",
++ "TX_FRAGS_LINEARIZED",
++ "TX_HW_CSUMMED",
++};
++
++static void gmac_dump_dma_state(struct net_device *netdev);
++
++static void gmac_update_config0_reg(struct net_device *netdev,
++ u32 val, u32 vmask)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg = (reg & ~vmask) | val;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_enable_tx_rx(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg &= ~CONFIG0_TX_RX_DISABLE;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_disable_tx_rx(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ val = readl(port->gmac_base + GMAC_CONFIG0);
++ val |= CONFIG0_TX_RX_DISABLE;
++ writel(val, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++
++ mdelay(10); /* let GMAC consume packet */
++}
++
++static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ val = readl(port->gmac_base + GMAC_CONFIG0);
++ val &= ~CONFIG0_FLOW_CTL;
++ if (tx)
++ val |= CONFIG0_FLOW_TX;
++ if (rx)
++ val |= CONFIG0_FLOW_RX;
++ writel(val, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++}
++
++static void gmac_speed_set(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct phy_device *phydev = netdev->phydev;
++ union gmac_status status, old_status;
++ int pause_tx = 0;
++ int pause_rx = 0;
++
++ status.bits32 = readl(port->gmac_base + GMAC_STATUS);
++ old_status.bits32 = status.bits32;
++ status.bits.link = phydev->link;
++ status.bits.duplex = phydev->duplex;
++
++ switch (phydev->speed) {
++ case 1000:
++ status.bits.speed = GMAC_SPEED_1000;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
++ netdev_info(netdev, "connect to RGMII @ 1Gbit\n");
++ break;
++ case 100:
++ status.bits.speed = GMAC_SPEED_100;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII @ 100 Mbit\n");
++ break;
++ case 10:
++ status.bits.speed = GMAC_SPEED_10;
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII @ 10 Mbit\n");
++ break;
++ default:
++ netdev_warn(netdev, "Not supported PHY speed (%d)\n",
++ phydev->speed);
++ }
++
++ if (phydev->duplex == DUPLEX_FULL) {
++ u16 lcladv = phy_read(phydev, MII_ADVERTISE);
++ u16 rmtadv = phy_read(phydev, MII_LPA);
++ u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
++
++ if (cap & FLOW_CTRL_RX)
++ pause_rx = 1;
++ if (cap & FLOW_CTRL_TX)
++ pause_tx = 1;
++ }
++
++ gmac_set_flow_control(netdev, pause_tx, pause_rx);
++
++ if (old_status.bits32 == status.bits32)
++ return;
++
++ if (netif_msg_link(port)) {
++ phy_print_status(phydev);
++ netdev_info(netdev, "link flow control: %s\n",
++ phydev->pause
++ ? (phydev->asym_pause ? "tx" : "both")
++ : (phydev->asym_pause ? "rx" : "none")
++ );
++ }
++
++ gmac_disable_tx_rx(netdev);
++ writel(status.bits32, port->gmac_base + GMAC_STATUS);
++ gmac_enable_tx_rx(netdev);
++}
++
++static int gmac_setup_phy(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_status status = { .bits32 = 0 };
++ struct device *dev = port->dev;
++ struct phy_device *phy;
++
++ phy = of_phy_get_and_connect(netdev,
++ dev->of_node,
++ gmac_speed_set);
++ if (!phy)
++ return -ENODEV;
++ netdev->phydev = phy;
++
++ netdev_info(netdev, "connected to PHY \"%s\"\n",
++ phydev_name(phy));
++ phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
++ (unsigned long)phy->phy_id,
++ phy_modes(phy->interface));
++
++ phy->supported &= PHY_GBIT_FEATURES;
++ phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
++ phy->advertising = phy->supported;
++
++ /* set PHY interface type */
++ switch (phy->interface) {
++ case PHY_INTERFACE_MODE_MII:
++ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
++ status.bits.mii_rmii = GMAC_PHY_MII;
++ netdev_info(netdev, "connect to MII\n");
++ break;
++ case PHY_INTERFACE_MODE_GMII:
++ netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
++ status.bits.mii_rmii = GMAC_PHY_GMII;
++ netdev_info(netdev, "connect to GMII\n");
++ break;
++ case PHY_INTERFACE_MODE_RGMII:
++ dev_info(dev, "set GMAC0 and GMAC1 to MII/RGMII mode\n");
++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
++ netdev_info(netdev, "connect to RGMII\n");
++ break;
++ default:
++ netdev_err(netdev, "Unsupported MII interface\n");
++ phy_disconnect(phy);
++ netdev->phydev = NULL;
++ return -EINVAL;
++ }
++ writel(status.bits32, port->gmac_base + GMAC_STATUS);
++
++ return 0;
++}
++
++static int gmac_pick_rx_max_len(int max_l3_len)
++{
++ /* index = CONFIG_MAXLEN_XXX values */
++ static const int max_len[8] = {
++ 1536, 1518, 1522, 1542,
++ 9212, 10236, 1518, 1518
++ };
++ int i, n = 5;
++
++ max_l3_len += ETH_HLEN + VLAN_HLEN;
++
++ if (max_l3_len > max_len[n])
++ return -1;
++
++ for (i = 0; i < 5; i++) {
++ if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
++ n = i;
++ }
++
++ return n;
++}
++
++static int gmac_init(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0 = { .bits = {
++ .dis_tx = 1,
++ .dis_rx = 1,
++ .ipv4_rx_chksum = 1,
++ .ipv6_rx_chksum = 1,
++ .rx_err_detect = 1,
++ .rgmm_edge = 1,
++ .port0_chk_hwq = 1,
++ .port1_chk_hwq = 1,
++ .port0_chk_toeq = 1,
++ .port1_chk_toeq = 1,
++ .port0_chk_classq = 1,
++ .port1_chk_classq = 1,
++ } };
++ union gmac_ahb_weight ahb_weight = { .bits = {
++ .rx_weight = 1,
++ .tx_weight = 1,
++ .hash_weight = 1,
++ .pre_req = 0x1f,
++ .tq_dv_threshold = 0,
++ } };
++ union gmac_tx_wcr0 hw_weigh = { .bits = {
++ .hw_tq3 = 1,
++ .hw_tq2 = 1,
++ .hw_tq1 = 1,
++ .hw_tq0 = 1,
++ } };
++ union gmac_tx_wcr1 sw_weigh = { .bits = {
++ .sw_tq5 = 1,
++ .sw_tq4 = 1,
++ .sw_tq3 = 1,
++ .sw_tq2 = 1,
++ .sw_tq1 = 1,
++ .sw_tq0 = 1,
++ } };
++ union gmac_config1 config1 = { .bits = {
++ .set_threshold = 16,
++ .rel_threshold = 24,
++ } };
++ union gmac_config2 config2 = { .bits = {
++ .set_threshold = 16,
++ .rel_threshold = 32,
++ } };
++ union gmac_config3 config3 = { .bits = {
++ .set_threshold = 0,
++ .rel_threshold = 0,
++ } };
++ union gmac_config0 tmp;
++ u32 val;
++
++ config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
++ tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++ config0.bits.reserved = tmp.bits.reserved;
++ writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
++ writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
++ writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
++ writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
++
++ val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
++ writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
++
++ writel(hw_weigh.bits32,
++ port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
++ writel(sw_weigh.bits32,
++ port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
++
++ port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
++ port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
++ port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
++
++ /* Mark every quarter of the queue a packet for interrupt
++ * in order to be able to wake up the queue if it was stopped
++ */
++ port->irq_every_tx_packets = 1 << (port->txq_order - 2);
++
++ return 0;
++}
++
++static void gmac_uninit(struct net_device *netdev)
++{
++ if (netdev->phydev)
++ phy_disconnect(netdev->phydev);
++}
++
++static int gmac_setup_txqs(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int n_txq = netdev->num_tx_queues;
++ struct gemini_ethernet *geth = port->geth;
++ size_t entries = 1 << port->txq_order;
++ struct gmac_txq *txq = port->txq;
++ struct gmac_txdesc *desc_ring;
++ size_t len = n_txq * entries;
++ struct sk_buff **skb_tab;
++ void __iomem *rwptr_reg;
++ unsigned int r;
++ int i;
++
++ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
++ if (!skb_tab)
++ return -ENOMEM;
++
++ desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
++ &port->txq_dma_base, GFP_KERNEL);
++
++ if (!desc_ring) {
++ kfree(skb_tab);
++ return -ENOMEM;
++ }
++
++ if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
++ dev_warn(geth->dev, "TX queue base it not aligned\n");
++ return -ENOMEM;
++ }
++
++ writel(port->txq_dma_base | port->txq_order,
++ port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
++
++ for (i = 0; i < n_txq; i++) {
++ txq->ring = desc_ring;
++ txq->skb = skb_tab;
++ txq->noirq_packets = 0;
++
++ r = readw(rwptr_reg);
++ rwptr_reg += 2;
++ writew(r, rwptr_reg);
++ rwptr_reg += 2;
++ txq->cptr = r;
++
++ txq++;
++ desc_ring += entries;
++ skb_tab += entries;
++ }
++
++ return 0;
++}
++
++static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
++ unsigned int r)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int m = (1 << port->txq_order) - 1;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int c = txq->cptr;
++ union gmac_txdesc_0 word0;
++ union gmac_txdesc_1 word1;
++ unsigned int hwchksum = 0;
++ unsigned long bytes = 0;
++ struct gmac_txdesc *txd;
++ unsigned short nfrags;
++ unsigned int errs = 0;
++ unsigned int pkts = 0;
++ unsigned int word3;
++ dma_addr_t mapping;
++
++ if (c == r)
++ return;
++
++ while (c != r) {
++ txd = txq->ring + c;
++ word0 = txd->word0;
++ word1 = txd->word1;
++ mapping = txd->word2.buf_adr;
++ word3 = txd->word3.bits32;
++
++ dma_unmap_single(geth->dev, mapping,
++ word0.bits.buffer_size, DMA_TO_DEVICE);
++
++ if (word3 & EOF_BIT)
++ dev_kfree_skb(txq->skb[c]);
++
++ c++;
++ c &= m;
++
++ if (!(word3 & SOF_BIT))
++ continue;
++
++ if (!word0.bits.status_tx_ok) {
++ errs++;
++ continue;
++ }
++
++ pkts++;
++ bytes += txd->word1.bits.byte_count;
++
++ if (word1.bits32 & TSS_CHECKUM_ENABLE)
++ hwchksum++;
++
++ nfrags = word0.bits.desc_count - 1;
++ if (nfrags) {
++ if (nfrags >= TX_MAX_FRAGS)
++ nfrags = TX_MAX_FRAGS - 1;
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->tx_frag_stats[nfrags]++;
++ u64_stats_update_end(&port->ir_stats_syncp);
++ }
++ }
++
++ u64_stats_update_begin(&port->ir_stats_syncp);
++ port->stats.tx_errors += errs;
++ port->stats.tx_packets += pkts;
++ port->stats.tx_bytes += bytes;
++ port->tx_hw_csummed += hwchksum;
++ u64_stats_update_end(&port->ir_stats_syncp);
++
++ txq->cptr = c;
++}
++
++static void gmac_cleanup_txqs(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int n_txq = netdev->num_tx_queues;
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *rwptr_reg;
++ unsigned int r, i;
++
++ rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ for (i = 0; i < n_txq; i++) {
++ r = readw(rwptr_reg);
++ rwptr_reg += 2;
++ writew(r, rwptr_reg);
++ rwptr_reg += 2;
++
++ gmac_clean_txq(netdev, port->txq + i, r);
++ }
++ writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
++
++ kfree(port->txq->skb);
++ dma_free_coherent(geth->dev,
++ n_txq * sizeof(*port->txq->ring) << port->txq_order,
++ port->txq->ring, port->txq_dma_base);
++}
++
++static int gmac_setup_rxq(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ struct nontoe_qhdr __iomem *qhdr;
++
++ qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
++ port->rxq_rwptr = &qhdr->word1;
++
++ /* Remap a slew of memory to use for the RX queue */
++ port->rxq_ring = dma_alloc_coherent(geth->dev,
++ sizeof(*port->rxq_ring) << port->rxq_order,
++ &port->rxq_dma_base, GFP_KERNEL);
++ if (!port->rxq_ring)
++ return -ENOMEM;
++ if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
++ dev_warn(geth->dev, "RX queue base it not aligned\n");
++ return -ENOMEM;
++ }
++
++ writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
++ writel(0, port->rxq_rwptr);
++ return 0;
++}
++
++static struct gmac_queue_page *
++gmac_get_queue_page(struct gemini_ethernet *geth,
++ struct gemini_ethernet_port *port,
++ dma_addr_t addr)
++{
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++ int i;
++
++ /* Only look for even pages */
++ mapping = addr & PAGE_MASK;
++
++ if (!geth->freeq_pages) {
++ dev_err(geth->dev, "try to get page with no page list\n");
++ return NULL;
++ }
++
++ /* Look up a ring buffer page from virtual mapping */
++ for (i = 0; i < geth->num_freeq_pages; i++) {
++ gpage = &geth->freeq_pages[i];
++ if (gpage->mapping == mapping)
++ return gpage;
++ }
++
++ return NULL;
++}
++
++static void gmac_cleanup_rxq(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ struct gmac_rxdesc *rxd = port->rxq_ring;
++ static struct gmac_queue_page *gpage;
++ struct nontoe_qhdr __iomem *qhdr;
++ void __iomem *dma_reg;
++ void __iomem *ptr_reg;
++ dma_addr_t mapping;
++ union dma_rwptr rw;
++ unsigned int r, w;
++
++ qhdr = geth->base +
++ TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
++ dma_reg = &qhdr->word0;
++ ptr_reg = &qhdr->word1;
++
++ rw.bits32 = readl(ptr_reg);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++ writew(r, ptr_reg + 2);
++
++ writel(0, dma_reg);
++
++ /* Loop from read pointer to write pointer of the RX queue
++ * and free up all pages by the queue.
++ */
++ while (r != w) {
++ mapping = rxd[r].word2.buf_adr;
++ r++;
++ r &= ((1 << port->rxq_order) - 1);
++
++ if (!mapping)
++ continue;
++
++ /* Freeq pointers are one page off */
++ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
++ if (!gpage) {
++ dev_err(geth->dev, "could not find page\n");
++ continue;
++ }
++ /* Release the RX queue reference to the page */
++ put_page(gpage->page);
++ }
++
++ dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
++ port->rxq_ring, port->rxq_dma_base);
++}
++
++static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
++ int pn)
++{
++ struct gmac_rxdesc *freeq_entry;
++ struct gmac_queue_page *gpage;
++ unsigned int fpp_order;
++ unsigned int frag_len;
++ dma_addr_t mapping;
++ struct page *page;
++ int i;
++
++ /* First allocate and DMA map a single page */
++ page = alloc_page(GFP_ATOMIC);
++ if (!page)
++ return NULL;
++
++ mapping = dma_map_single(geth->dev, page_address(page),
++ PAGE_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(geth->dev, mapping)) {
++ put_page(page);
++ return NULL;
++ }
++
++ /* The assign the page mapping (physical address) to the buffer address
++ * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
++ * 4k), and the default RX frag order is 11 (fragments are up 20 2048
++ * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
++ * each page normally needs two entries in the queue.
++ */
++ frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
++ fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ freeq_entry = geth->freeq_ring + (pn << fpp_order);
++ dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
++ pn, frag_len, (1 << fpp_order), freeq_entry);
++ for (i = (1 << fpp_order); i > 0; i--) {
++ freeq_entry->word2.buf_adr = mapping;
++ freeq_entry++;
++ mapping += frag_len;
++ }
++
++ /* If the freeq entry already has a page mapped, then unmap it. */
++ gpage = &geth->freeq_pages[pn];
++ if (gpage->page) {
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++ /* This should be the last reference to the page so it gets
++ * released
++ */
++ put_page(gpage->page);
++ }
++
++ /* Then put our new mapping into the page table */
++ dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
++ pn, (unsigned int)mapping, page);
++ gpage->mapping = mapping;
++ gpage->page = page;
++
++ return page;
++}
++
++/**
++ * geth_fill_freeq() - Fill the freeq with empty fragments to use
++ * @geth: the ethernet adapter
++ * @refill: whether to reset the queue by filling in all freeq entries or
++ * just refill it, usually the interrupt to refill the queue happens when
++ * the queue is half empty.
++ */
++static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int count = 0;
++ unsigned int pn, epn;
++ unsigned long flags;
++ union dma_rwptr rw;
++ unsigned int m_pn;
++
++ /* Mask for page */
++ m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
++
++ spin_lock_irqsave(&geth->freeq_lock, flags);
++
++ rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
++ pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
++ epn = (rw.bits.rptr >> fpp_order) - 1;
++ epn &= m_pn;
++
++ /* Loop over the freeq ring buffer entries */
++ while (pn != epn) {
++ struct gmac_queue_page *gpage;
++ struct page *page;
++
++ gpage = &geth->freeq_pages[pn];
++ page = gpage->page;
++
++ dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
++ pn, page_ref_count(page), 1 << fpp_order);
++
++ if (page_ref_count(page) > 1) {
++ unsigned int fl = (pn - epn) & m_pn;
++
++ if (fl > 64 >> fpp_order)
++ break;
++
++ page = geth_freeq_alloc_map_page(geth, pn);
++ if (!page)
++ break;
++ }
++
++ /* Add one reference per fragment in the page */
++ page_ref_add(page, 1 << fpp_order);
++ count += 1 << fpp_order;
++ pn++;
++ pn &= m_pn;
++ }
++
++ writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
++
++ spin_unlock_irqrestore(&geth->freeq_lock, flags);
++
++ return count;
++}
++
++static int geth_setup_freeq(struct gemini_ethernet *geth)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int frag_len = 1 << geth->freeq_frag_order;
++ unsigned int len = 1 << geth->freeq_order;
++ unsigned int pages = len >> fpp_order;
++ union queue_threshold qt;
++ union dma_skb_size skbsz;
++ unsigned int filled;
++ unsigned int pn;
++
++ geth->freeq_ring = dma_alloc_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ &geth->freeq_dma_base, GFP_KERNEL);
++ if (!geth->freeq_ring)
++ return -ENOMEM;
++ if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
++ dev_warn(geth->dev, "queue ring base it not aligned\n");
++ goto err_freeq;
++ }
++
++ /* Allocate a mapping to page look-up index */
++ geth->freeq_pages = kzalloc(pages * sizeof(*geth->freeq_pages),
++ GFP_KERNEL);
++ if (!geth->freeq_pages)
++ goto err_freeq;
++ geth->num_freeq_pages = pages;
++
++ dev_info(geth->dev, "allocate %d pages for queue\n", pages);
++ for (pn = 0; pn < pages; pn++)
++ if (!geth_freeq_alloc_map_page(geth, pn))
++ goto err_freeq_alloc;
++
++ filled = geth_fill_freeq(geth, false);
++ if (!filled)
++ goto err_freeq_alloc;
++
++ qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
++ qt.bits.swfq_empty = 32;
++ writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
++
++ skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
++ writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
++ writel(geth->freeq_dma_base | geth->freeq_order,
++ geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++
++ return 0;
++
++err_freeq_alloc:
++ while (pn > 0) {
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++
++ --pn;
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++ gpage = &geth->freeq_pages[pn];
++ put_page(gpage->page);
++ }
++
++ kfree(geth->freeq_pages);
++err_freeq:
++ dma_free_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ geth->freeq_ring, geth->freeq_dma_base);
++ geth->freeq_ring = NULL;
++ return -ENOMEM;
++}
++
++/**
++ * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
++ * @geth: the Gemini global ethernet state
++ */
++static void geth_cleanup_freeq(struct gemini_ethernet *geth)
++{
++ unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
++ unsigned int frag_len = 1 << geth->freeq_frag_order;
++ unsigned int len = 1 << geth->freeq_order;
++ unsigned int pages = len >> fpp_order;
++ unsigned int pn;
++
++ writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
++ geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
++ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++
++ for (pn = 0; pn < pages; pn++) {
++ struct gmac_queue_page *gpage;
++ dma_addr_t mapping;
++
++ mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
++ dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
++
++ gpage = &geth->freeq_pages[pn];
++ while (page_ref_count(gpage->page) > 0)
++ put_page(gpage->page);
++ }
++
++ kfree(geth->freeq_pages);
++
++ dma_free_coherent(geth->dev,
++ sizeof(*geth->freeq_ring) << geth->freeq_order,
++ geth->freeq_ring, geth->freeq_dma_base);
++}
++
++/**
++ * geth_resize_freeq() - resize the software queue depth
++ * @port: the port requesting the change
++ *
++ * This gets called at least once during probe() so the device queue gets
++ * "resized" from the hardware defaults. Since both ports/net devices share
++ * the same hardware queue, some synchronization between the ports is
++ * needed.
++ */
++static int geth_resize_freeq(struct gemini_ethernet_port *port)
++{
++ struct gemini_ethernet *geth = port->geth;
++ struct net_device *netdev = port->netdev;
++ struct gemini_ethernet_port *other_port;
++ struct net_device *other_netdev;
++ unsigned int new_size = 0;
++ unsigned int new_order;
++ unsigned long flags;
++ u32 en;
++ int ret;
++
++ if (netdev->dev_id == 0)
++ other_netdev = geth->port1->netdev;
++ else
++ other_netdev = geth->port0->netdev;
++
++ if (other_netdev && netif_running(other_netdev))
++ return -EBUSY;
++
++ new_size = 1 << (port->rxq_order + 1);
++ netdev_dbg(netdev, "port %d size: %d order %d\n",
++ netdev->dev_id,
++ new_size,
++ port->rxq_order);
++ if (other_netdev) {
++ other_port = netdev_priv(other_netdev);
++ new_size += 1 << (other_port->rxq_order + 1);
++ netdev_dbg(other_netdev, "port %d size: %d order %d\n",
++ other_netdev->dev_id,
++ (1 << (other_port->rxq_order + 1)),
++ other_port->rxq_order);
++ }
++
++ new_order = min(15, ilog2(new_size - 1) + 1);
++ dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
++ new_size, new_order);
++ if (geth->freeq_order == new_order)
++ return 0;
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
++ /* Disable the software queue IRQs */
++ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ en &= ~SWFQ_EMPTY_INT_BIT;
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ /* Drop the old queue */
++ if (geth->freeq_ring)
++ geth_cleanup_freeq(geth);
++
++ /* Allocate a new queue with the desired order */
++ geth->freeq_order = new_order;
++ ret = geth_setup_freeq(geth);
++
++ /* Restart the interrupts - NOTE if this is the first resize
++ * after probe(), this is where the interrupts get turned on
++ * in the first place.
++ */
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ en |= SWFQ_EMPTY_INT_BIT;
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ return ret;
++}
++
++static void gmac_tx_irq_enable(struct net_device *netdev,
++ unsigned int txq, int en)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ u32 val, mask;
++
++ netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
++
++ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
++
++ if (en)
++ writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ val = en ? val | mask : val & ~mask;
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++}
++
++static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
++{
++ struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
++
++ gmac_tx_irq_enable(netdev, txq_num, 0);
++ netif_tx_wake_queue(ntxq);
++}
++
++static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
++ struct gmac_txq *txq, unsigned short *desc)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct skb_shared_info *skb_si = skb_shinfo(skb);
++ unsigned short m = (1 << port->txq_order) - 1;
++ short frag, last_frag = skb_si->nr_frags - 1;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int word1, word3, buflen;
++ unsigned short w = *desc;
++ struct gmac_txdesc *txd;
++ skb_frag_t *skb_frag;
++ dma_addr_t mapping;
++ unsigned short mtu;
++ void *buffer;
++
++ mtu = ETH_HLEN;
++ mtu += netdev->mtu;
++ if (skb->protocol == htons(ETH_P_8021Q))
++ mtu += VLAN_HLEN;
++
++ word1 = skb->len;
++ word3 = SOF_BIT;
++
++ if (word1 > mtu) {
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mtu;
++ }
++
++ if (skb->ip_summed != CHECKSUM_NONE) {
++ int tcp = 0;
++
++ if (skb->protocol == htons(ETH_P_IP)) {
++ word1 |= TSS_IP_CHKSUM_BIT;
++ tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
++ } else { /* IPv6 */
++ word1 |= TSS_IPV6_ENABLE_BIT;
++ tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
++ }
++
++ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
++ }
++
++ frag = -1;
++ while (frag <= last_frag) {
++ if (frag == -1) {
++ buffer = skb->data;
++ buflen = skb_headlen(skb);
++ } else {
++ skb_frag = skb_si->frags + frag;
++ buffer = page_address(skb_frag_page(skb_frag)) +
++ skb_frag->page_offset;
++ buflen = skb_frag->size;
++ }
++
++ if (frag == last_frag) {
++ word3 |= EOF_BIT;
++ txq->skb[w] = skb;
++ }
++
++ mapping = dma_map_single(geth->dev, buffer, buflen,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(geth->dev, mapping))
++ goto map_error;
++
++ txd = txq->ring + w;
++ txd->word0.bits32 = buflen;
++ txd->word1.bits32 = word1;
++ txd->word2.buf_adr = mapping;
++ txd->word3.bits32 = word3;
++
++ word3 &= MTU_SIZE_BIT_MASK;
++ w++;
++ w &= m;
++ frag++;
++ }
++
++ *desc = w;
++ return 0;
++
++map_error:
++ while (w != *desc) {
++ w--;
++ w &= m;
++
++ dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
++ txq->ring[w].word0.bits.buffer_size,
++ DMA_TO_DEVICE);
++ }
++ return -ENOMEM;
++}
++
++static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned short m = (1 << port->txq_order) - 1;
++ struct netdev_queue *ntxq;
++ unsigned short r, w, d;
++ void __iomem *ptr_reg;
++ struct gmac_txq *txq;
++ int txq_num, nfrags;
++ union dma_rwptr rw;
++
++ SKB_FRAG_ASSERT(skb);
++
++ if (skb->len >= 0x10000)
++ goto out_drop_free;
++
++ txq_num = skb_get_queue_mapping(skb);
++ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
++ txq = &port->txq[txq_num];
++ ntxq = netdev_get_tx_queue(netdev, txq_num);
++ nfrags = skb_shinfo(skb)->nr_frags;
++
++ rw.bits32 = readl(ptr_reg);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++
++ d = txq->cptr - w - 1;
++ d &= m;
++
++ if (d < nfrags + 2) {
++ gmac_clean_txq(netdev, txq, r);
++ d = txq->cptr - w - 1;
++ d &= m;
++
++ if (d < nfrags + 2) {
++ netif_tx_stop_queue(ntxq);
++
++ d = txq->cptr + nfrags + 16;
++ d &= m;
++ txq->ring[d].word3.bits.eofie = 1;
++ gmac_tx_irq_enable(netdev, txq_num, 1);
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ netdev->stats.tx_fifo_errors++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++ return NETDEV_TX_BUSY;
++ }
++ }
++
++ if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
++ if (skb_linearize(skb))
++ goto out_drop;
++
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->tx_frags_linearized++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++
++ if (gmac_map_tx_bufs(netdev, skb, txq, &w))
++ goto out_drop_free;
++ }
++
++ writew(w, ptr_reg + 2);
++
++ gmac_clean_txq(netdev, txq, r);
++ return NETDEV_TX_OK;
++
++out_drop_free:
++ dev_kfree_skb(skb);
++out_drop:
++ u64_stats_update_begin(&port->tx_stats_syncp);
++ port->stats.tx_dropped++;
++ u64_stats_update_end(&port->tx_stats_syncp);
++ return NETDEV_TX_OK;
++}
++
++static void gmac_tx_timeout(struct net_device *netdev)
++{
++ netdev_err(netdev, "Tx timeout\n");
++ gmac_dump_dma_state(netdev);
++}
++
++static void gmac_enable_irq(struct net_device *netdev, int enable)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++ u32 val, mask;
++
++ netdev_info(netdev, "%s device %d %s\n", __func__,
++ netdev->dev_id, enable ? "enable" : "disable");
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
++ mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++
++ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++
++ mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++ u32 val, mask;
++
++ netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
++ enable ? "enable" : "disable");
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ val = enable ? (val | mask) : (val & ~mask);
++ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
++ union gmac_rxdesc_0 word0,
++ unsigned int frame_len)
++{
++ unsigned int rx_csum = word0.bits.chksum_status;
++ unsigned int rx_status = word0.bits.status;
++ struct sk_buff *skb = NULL;
++
++ port->rx_stats[rx_status]++;
++ port->rx_csum_stats[rx_csum]++;
++
++ if (word0.bits.derr || word0.bits.perr ||
++ rx_status || frame_len < ETH_ZLEN ||
++ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
++ port->stats.rx_errors++;
++
++ if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
++ port->stats.rx_length_errors++;
++ if (RX_ERROR_OVER(rx_status))
++ port->stats.rx_over_errors++;
++ if (RX_ERROR_CRC(rx_status))
++ port->stats.rx_crc_errors++;
++ if (RX_ERROR_FRAME(rx_status))
++ port->stats.rx_frame_errors++;
++ return NULL;
++ }
++
++ skb = napi_get_frags(&port->napi);
++ if (!skb)
++ goto update_exit;
++
++ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++
++update_exit:
++ port->stats.rx_bytes += frame_len;
++ port->stats.rx_packets++;
++ return skb;
++}
++
++static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned short m = (1 << port->rxq_order) - 1;
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *ptr_reg = port->rxq_rwptr;
++ unsigned int frame_len, frag_len;
++ struct gmac_rxdesc *rx = NULL;
++ struct gmac_queue_page *gpage;
++ static struct sk_buff *skb;
++ union gmac_rxdesc_0 word0;
++ union gmac_rxdesc_1 word1;
++ union gmac_rxdesc_3 word3;
++ struct page *page = NULL;
++ unsigned int page_offs;
++ unsigned short r, w;
++ union dma_rwptr rw;
++ dma_addr_t mapping;
++ int frag_nr = 0;
++
++ rw.bits32 = readl(ptr_reg);
++ /* Reset interrupt as all packages until here are taken into account */
++ writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
++ geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ r = rw.bits.rptr;
++ w = rw.bits.wptr;
++
++ while (budget && w != r) {
++ rx = port->rxq_ring + r;
++ word0 = rx->word0;
++ word1 = rx->word1;
++ mapping = rx->word2.buf_adr;
++ word3 = rx->word3;
++
++ r++;
++ r &= m;
++
++ frag_len = word0.bits.buffer_size;
++ frame_len = word1.bits.byte_count;
++ page_offs = mapping & ~PAGE_MASK;
++
++ if (!mapping) {
++ netdev_err(netdev,
++ "rxq[%u]: HW BUG: zero DMA desc\n", r);
++ goto err_drop;
++ }
++
++ /* Freeq pointers are one page off */
++ gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
++ if (!gpage) {
++ dev_err(geth->dev, "could not find mapping\n");
++ continue;
++ }
++ page = gpage->page;
++
++ if (word3.bits32 & SOF_BIT) {
++ if (skb) {
++ napi_free_frags(&port->napi);
++ port->stats.rx_dropped++;
++ }
++
++ skb = gmac_skb_if_good_frame(port, word0, frame_len);
++ if (!skb)
++ goto err_drop;
++
++ page_offs += NET_IP_ALIGN;
++ frag_len -= NET_IP_ALIGN;
++ frag_nr = 0;
++
++ } else if (!skb) {
++ put_page(page);
++ continue;
++ }
++
++ if (word3.bits32 & EOF_BIT)
++ frag_len = frame_len - skb->len;
++
++ /* append page frag to skb */
++ if (frag_nr == MAX_SKB_FRAGS)
++ goto err_drop;
++
++ if (frag_len == 0)
++ netdev_err(netdev, "Received fragment with len = 0\n");
++
++ skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
++ skb->len += frag_len;
++ skb->data_len += frag_len;
++ skb->truesize += frag_len;
++ frag_nr++;
++
++ if (word3.bits32 & EOF_BIT) {
++ napi_gro_frags(&port->napi);
++ skb = NULL;
++ --budget;
++ }
++ continue;
++
++err_drop:
++ if (skb) {
++ napi_free_frags(&port->napi);
++ skb = NULL;
++ }
++
++ if (mapping)
++ put_page(page);
++
++ port->stats.rx_dropped++;
++ }
++
++ writew(r, ptr_reg);
++ return budget;
++}
++
++static int gmac_napi_poll(struct napi_struct *napi, int budget)
++{
++ struct gemini_ethernet_port *port = netdev_priv(napi->dev);
++ struct gemini_ethernet *geth = port->geth;
++ unsigned int freeq_threshold;
++ unsigned int received;
++
++ freeq_threshold = 1 << (geth->freeq_order - 1);
++ u64_stats_update_begin(&port->rx_stats_syncp);
++
++ received = gmac_rx(napi->dev, budget);
++ if (received < budget) {
++ napi_gro_flush(napi, false);
++ napi_complete_done(napi, received);
++ gmac_enable_rx_irq(napi->dev, 1);
++ ++port->rx_napi_exits;
++ }
++
++ port->freeq_refill += (budget - received);
++ if (port->freeq_refill > freeq_threshold) {
++ port->freeq_refill -= freeq_threshold;
++ geth_fill_freeq(geth, true);
++ }
++
++ u64_stats_update_end(&port->rx_stats_syncp);
++ return received;
++}
++
++static void gmac_dump_dma_state(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *ptr_reg;
++ u32 reg[5];
++
++ /* Interrupt status */
++ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
++ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
++ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3], reg[4]);
++
++ /* Interrupt enable */
++ reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
++ reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
++ reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3], reg[4]);
++
++ /* RX DMA status */
++ reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
++ reg[2] = GET_RPTR(port->rxq_rwptr);
++ reg[3] = GET_WPTR(port->rxq_rwptr);
++ netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
++ reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
++ reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
++ netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ /* TX DMA status */
++ ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
++ reg[2] = GET_RPTR(ptr_reg);
++ reg[3] = GET_WPTR(ptr_reg);
++ netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
++ reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
++ reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
++ reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
++ netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ reg[0], reg[1], reg[2], reg[3]);
++
++ /* FREE queues status */
++ ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
++
++ reg[0] = GET_RPTR(ptr_reg);
++ reg[1] = GET_WPTR(ptr_reg);
++
++ ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
++
++ reg[2] = GET_RPTR(ptr_reg);
++ reg[3] = GET_WPTR(ptr_reg);
++ netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
++ reg[0], reg[1], reg[2], reg[3]);
++}
++
++static void gmac_update_hw_stats(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int rx_discards, rx_mcast, rx_bcast;
++ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ u64_stats_update_begin(&port->ir_stats_syncp);
++
++ rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
++ port->hw_stats[0] += rx_discards;
++ port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
++ rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
++ port->hw_stats[2] += rx_mcast;
++ rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
++ port->hw_stats[3] += rx_bcast;
++ port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
++ port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
++
++ port->stats.rx_missed_errors += rx_discards;
++ port->stats.multicast += rx_mcast;
++ port->stats.multicast += rx_bcast;
++
++ writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
++ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ u64_stats_update_end(&port->ir_stats_syncp);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++}
++
++/**
++ * gmac_get_intr_flags() - get interrupt status flags for a port from
++ * @netdev: the net device for the port to get flags from
++ * @i: the interrupt status register 0..4
++ */
++static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ struct gemini_ethernet *geth = port->geth;
++ void __iomem *irqif_reg, *irqen_reg;
++ unsigned int offs, val;
++
++ /* Calculate the offset using the stride of the status registers */
++ offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
++ GLOBAL_INTERRUPT_STATUS_0_REG);
++
++ irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
++ irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
++
++ val = readl(irqif_reg) & readl(irqen_reg);
++ return val;
++}
++
++static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
++{
++ struct gemini_ethernet_port *port =
++ container_of(timer, struct gemini_ethernet_port,
++ rx_coalesce_timer);
++
++ napi_schedule(&port->napi);
++ return HRTIMER_NORESTART;
++}
++
++static irqreturn_t gmac_irq(int irq, void *data)
++{
++ struct gemini_ethernet_port *port;
++ struct net_device *netdev = data;
++ struct gemini_ethernet *geth;
++ u32 val, orr = 0;
++
++ port = netdev_priv(netdev);
++ geth = port->geth;
++
++ val = gmac_get_intr_flags(netdev, 0);
++ orr |= val;
++
++ if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
++ /* Oh, crap */
++ netdev_err(netdev, "hw failure/sw bug\n");
++ gmac_dump_dma_state(netdev);
++
++ /* don't know how to recover, just reduce losses */
++ gmac_enable_irq(netdev, 0);
++ return IRQ_HANDLED;
++ }
++
++ if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
++ gmac_tx_irq(netdev, 0);
++
++ val = gmac_get_intr_flags(netdev, 1);
++ orr |= val;
++
++ if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
++ gmac_enable_rx_irq(netdev, 0);
++
++ if (!port->rx_coalesce_nsecs) {
++ napi_schedule(&port->napi);
++ } else {
++ ktime_t ktime;
++
++ ktime = ktime_set(0, port->rx_coalesce_nsecs);
++ hrtimer_start(&port->rx_coalesce_timer, ktime,
++ HRTIMER_MODE_REL);
++ }
++ }
++
++ val = gmac_get_intr_flags(netdev, 4);
++ orr |= val;
++
++ if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
++ gmac_update_hw_stats(netdev);
++
++ if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
++ writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
++ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ spin_lock(&geth->irq_lock);
++ u64_stats_update_begin(&port->ir_stats_syncp);
++ ++port->stats.rx_fifo_errors;
++ u64_stats_update_end(&port->ir_stats_syncp);
++ spin_unlock(&geth->irq_lock);
++ }
++
++ return orr ? IRQ_HANDLED : IRQ_NONE;
++}
++
++static void gmac_start_dma(struct gemini_ethernet_port *port)
++{
++ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
++ union gmac_dma_ctrl dma_ctrl;
++
++ dma_ctrl.bits32 = readl(dma_ctrl_reg);
++ dma_ctrl.bits.rd_enable = 1;
++ dma_ctrl.bits.td_enable = 1;
++ dma_ctrl.bits.loopback = 0;
++ dma_ctrl.bits.drop_small_ack = 0;
++ dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
++ dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
++ dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
++ dma_ctrl.bits.rd_bus = HSIZE_8;
++ dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
++ dma_ctrl.bits.td_burst_size = HBURST_INCR8;
++ dma_ctrl.bits.td_bus = HSIZE_8;
++
++ writel(dma_ctrl.bits32, dma_ctrl_reg);
++}
++
++static void gmac_stop_dma(struct gemini_ethernet_port *port)
++{
++ void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
++ union gmac_dma_ctrl dma_ctrl;
++
++ dma_ctrl.bits32 = readl(dma_ctrl_reg);
++ dma_ctrl.bits.rd_enable = 0;
++ dma_ctrl.bits.td_enable = 0;
++ writel(dma_ctrl.bits32, dma_ctrl_reg);
++}
++
++static int gmac_open(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int err;
++
++ if (!netdev->phydev) {
++ err = gmac_setup_phy(netdev);
++ if (err) {
++ netif_err(port, ifup, netdev,
++ "PHY init failed: %d\n", err);
++ return err;
++ }
++ }
++
++ err = request_irq(netdev->irq, gmac_irq,
++ IRQF_SHARED, netdev->name, netdev);
++ if (err) {
++ netdev_err(netdev, "no IRQ\n");
++ return err;
++ }
++
++ netif_carrier_off(netdev);
++ phy_start(netdev->phydev);
++
++ err = geth_resize_freeq(port);
++ if (err) {
++ netdev_err(netdev, "could not resize freeq\n");
++ goto err_stop_phy;
++ }
++
++ err = gmac_setup_rxq(netdev);
++ if (err) {
++ netdev_err(netdev, "could not setup RXQ\n");
++ goto err_stop_phy;
++ }
++
++ err = gmac_setup_txqs(netdev);
++ if (err) {
++ netdev_err(netdev, "could not setup TXQs\n");
++ gmac_cleanup_rxq(netdev);
++ goto err_stop_phy;
++ }
++
++ napi_enable(&port->napi);
++
++ gmac_start_dma(port);
++ gmac_enable_irq(netdev, 1);
++ gmac_enable_tx_rx(netdev);
++ netif_tx_start_all_queues(netdev);
++
++ hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
++
++ netdev_info(netdev, "opened\n");
++
++ return 0;
++
++err_stop_phy:
++ phy_stop(netdev->phydev);
++ free_irq(netdev->irq, netdev);
++ return err;
++}
++
++static int gmac_stop(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ hrtimer_cancel(&port->rx_coalesce_timer);
++ netif_tx_stop_all_queues(netdev);
++ gmac_disable_tx_rx(netdev);
++ gmac_stop_dma(port);
++ napi_disable(&port->napi);
++
++ gmac_enable_irq(netdev, 0);
++ gmac_cleanup_rxq(netdev);
++ gmac_cleanup_txqs(netdev);
++
++ phy_stop(netdev->phydev);
++ free_irq(netdev->irq, netdev);
++
++ gmac_update_hw_stats(netdev);
++ return 0;
++}
++
++static void gmac_set_rx_mode(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_rx_fltr filter = { .bits = {
++ .broadcast = 1,
++ .multicast = 1,
++ .unicast = 1,
++ } };
++ struct netdev_hw_addr *ha;
++ unsigned int bit_nr;
++ u32 mc_filter[2];
++
++ mc_filter[1] = 0;
++ mc_filter[0] = 0;
++
++ if (netdev->flags & IFF_PROMISC) {
++ filter.bits.error = 1;
++ filter.bits.promiscuous = 1;
++ mc_filter[1] = ~0;
++ mc_filter[0] = ~0;
++ } else if (netdev->flags & IFF_ALLMULTI) {
++ mc_filter[1] = ~0;
++ mc_filter[0] = ~0;
++ } else {
++ netdev_for_each_mc_addr(ha, netdev) {
++ bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
++ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
++ }
++ }
++
++ writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
++ writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
++ writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
++}
++
++static void gmac_write_mac_address(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ __le32 addr[3];
++
++ memset(addr, 0, sizeof(addr));
++ memcpy(addr, netdev->dev_addr, ETH_ALEN);
++
++ writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
++ writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
++ writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
++}
++
++static int gmac_set_mac_address(struct net_device *netdev, void *addr)
++{
++ struct sockaddr *sa = addr;
++
++ memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
++ gmac_write_mac_address(netdev);
++
++ return 0;
++}
++
++static void gmac_clear_hw_stats(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ readl(port->gmac_base + GMAC_IN_DISCARDS);
++ readl(port->gmac_base + GMAC_IN_ERRORS);
++ readl(port->gmac_base + GMAC_IN_MCAST);
++ readl(port->gmac_base + GMAC_IN_BCAST);
++ readl(port->gmac_base + GMAC_IN_MAC1);
++ readl(port->gmac_base + GMAC_IN_MAC2);
++}
++
++static void gmac_get_stats64(struct net_device *netdev,
++ struct rtnl_link_stats64 *stats)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int start;
++
++ gmac_update_hw_stats(netdev);
++
++ /* Racing with RX NAPI */
++ do {
++ start = u64_stats_fetch_begin(&port->rx_stats_syncp);
++
++ stats->rx_packets = port->stats.rx_packets;
++ stats->rx_bytes = port->stats.rx_bytes;
++ stats->rx_errors = port->stats.rx_errors;
++ stats->rx_dropped = port->stats.rx_dropped;
++
++ stats->rx_length_errors = port->stats.rx_length_errors;
++ stats->rx_over_errors = port->stats.rx_over_errors;
++ stats->rx_crc_errors = port->stats.rx_crc_errors;
++ stats->rx_frame_errors = port->stats.rx_frame_errors;
++
++ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
++
++ /* Racing with MIB and TX completion interrupts */
++ do {
++ start = u64_stats_fetch_begin(&port->ir_stats_syncp);
++
++ stats->tx_errors = port->stats.tx_errors;
++ stats->tx_packets = port->stats.tx_packets;
++ stats->tx_bytes = port->stats.tx_bytes;
++
++ stats->multicast = port->stats.multicast;
++ stats->rx_missed_errors = port->stats.rx_missed_errors;
++ stats->rx_fifo_errors = port->stats.rx_fifo_errors;
++
++ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
++
++ /* Racing with hard_start_xmit */
++ do {
++ start = u64_stats_fetch_begin(&port->tx_stats_syncp);
++
++ stats->tx_dropped = port->stats.tx_dropped;
++
++ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
++
++ stats->rx_dropped += stats->rx_missed_errors;
++}
++
++static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
++{
++ int max_len = gmac_pick_rx_max_len(new_mtu);
++
++ if (max_len < 0)
++ return -EINVAL;
++
++ gmac_disable_tx_rx(netdev);
++
++ netdev->mtu = new_mtu;
++ gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
++ CONFIG0_MAXLEN_MASK);
++
++ netdev_update_features(netdev);
++
++ gmac_enable_tx_rx(netdev);
++
++ return 0;
++}
++
++static netdev_features_t gmac_fix_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
++ features &= ~GMAC_OFFLOAD_FEATURES;
++
++ return features;
++}
++
++static int gmac_set_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int enable = features & NETIF_F_RXCSUM;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&port->config_lock, flags);
++
++ reg = readl(port->gmac_base + GMAC_CONFIG0);
++ reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
++ writel(reg, port->gmac_base + GMAC_CONFIG0);
++
++ spin_unlock_irqrestore(&port->config_lock, flags);
++ return 0;
++}
++
++static int gmac_get_sset_count(struct net_device *netdev, int sset)
++{
++ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
++}
++
++static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
++{
++ if (stringset != ETH_SS_STATS)
++ return;
++
++ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
++}
++
++static void gmac_get_ethtool_stats(struct net_device *netdev,
++ struct ethtool_stats *estats, u64 *values)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ unsigned int start;
++ u64 *p;
++ int i;
++
++ gmac_update_hw_stats(netdev);
++
++ /* Racing with MIB interrupt */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->ir_stats_syncp);
++
++ for (i = 0; i < RX_STATS_NUM; i++)
++ *p++ = port->hw_stats[i];
++
++ } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
++ values = p;
++
++ /* Racing with RX NAPI */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->rx_stats_syncp);
++
++ for (i = 0; i < RX_STATUS_NUM; i++)
++ *p++ = port->rx_stats[i];
++ for (i = 0; i < RX_CHKSUM_NUM; i++)
++ *p++ = port->rx_csum_stats[i];
++ *p++ = port->rx_napi_exits;
++
++ } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
++ values = p;
++
++ /* Racing with TX start_xmit */
++ do {
++ p = values;
++ start = u64_stats_fetch_begin(&port->tx_stats_syncp);
++
++ for (i = 0; i < TX_MAX_FRAGS; i++) {
++ *values++ = port->tx_frag_stats[i];
++ port->tx_frag_stats[i] = 0;
++ }
++ *values++ = port->tx_frags_linearized;
++ *values++ = port->tx_hw_csummed;
++
++ } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
++}
++
++static int gmac_get_ksettings(struct net_device *netdev,
++ struct ethtool_link_ksettings *cmd)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ phy_ethtool_ksettings_get(netdev->phydev, cmd);
++
++ return 0;
++}
++
++static int gmac_set_ksettings(struct net_device *netdev,
++ const struct ethtool_link_ksettings *cmd)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ return phy_ethtool_ksettings_set(netdev->phydev, cmd);
++}
++
++static int gmac_nway_reset(struct net_device *netdev)
++{
++ if (!netdev->phydev)
++ return -ENXIO;
++ return phy_start_aneg(netdev->phydev);
++}
++
++static void gmac_get_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pparam)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0;
++
++ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++
++ pparam->rx_pause = config0.bits.rx_fc_en;
++ pparam->tx_pause = config0.bits.tx_fc_en;
++ pparam->autoneg = true;
++}
++
++static void gmac_get_ringparam(struct net_device *netdev,
++ struct ethtool_ringparam *rp)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ union gmac_config0 config0;
++
++ config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
++
++ rp->rx_max_pending = 1 << 15;
++ rp->rx_mini_max_pending = 0;
++ rp->rx_jumbo_max_pending = 0;
++ rp->tx_max_pending = 1 << 15;
++
++ rp->rx_pending = 1 << port->rxq_order;
++ rp->rx_mini_pending = 0;
++ rp->rx_jumbo_pending = 0;
++ rp->tx_pending = 1 << port->txq_order;
++}
++
++static int gmac_set_ringparam(struct net_device *netdev,
++ struct ethtool_ringparam *rp)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++ int err = 0;
++
++ if (netif_running(netdev))
++ return -EBUSY;
++
++ if (rp->rx_pending) {
++ port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
++ err = geth_resize_freeq(port);
++ }
++ if (rp->tx_pending) {
++ port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
++ port->irq_every_tx_packets = 1 << (port->txq_order - 2);
++ }
++
++ return err;
++}
++
++static int gmac_get_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ecmd)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ ecmd->rx_max_coalesced_frames = 1;
++ ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
++ ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
++
++ return 0;
++}
++
++static int gmac_set_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ecmd)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ if (ecmd->tx_max_coalesced_frames < 1)
++ return -EINVAL;
++ if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
++ return -EINVAL;
++
++ port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
++ port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
++
++ return 0;
++}
++
++static u32 gmac_get_msglevel(struct net_device *netdev)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ return port->msg_enable;
++}
++
++static void gmac_set_msglevel(struct net_device *netdev, u32 level)
++{
++ struct gemini_ethernet_port *port = netdev_priv(netdev);
++
++ port->msg_enable = level;
++}
++
++static void gmac_get_drvinfo(struct net_device *netdev,
++ struct ethtool_drvinfo *info)
++{
++ strcpy(info->driver, DRV_NAME);
++ strcpy(info->version, DRV_VERSION);
++ strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
++}
++
++static const struct net_device_ops gmac_351x_ops = {
++ .ndo_init = gmac_init,
++ .ndo_uninit = gmac_uninit,
++ .ndo_open = gmac_open,
++ .ndo_stop = gmac_stop,
++ .ndo_start_xmit = gmac_start_xmit,
++ .ndo_tx_timeout = gmac_tx_timeout,
++ .ndo_set_rx_mode = gmac_set_rx_mode,
++ .ndo_set_mac_address = gmac_set_mac_address,
++ .ndo_get_stats64 = gmac_get_stats64,
++ .ndo_change_mtu = gmac_change_mtu,
++ .ndo_fix_features = gmac_fix_features,
++ .ndo_set_features = gmac_set_features,
++};
++
++static const struct ethtool_ops gmac_351x_ethtool_ops = {
++ .get_sset_count = gmac_get_sset_count,
++ .get_strings = gmac_get_strings,
++ .get_ethtool_stats = gmac_get_ethtool_stats,
++ .get_link = ethtool_op_get_link,
++ .get_link_ksettings = gmac_get_ksettings,
++ .set_link_ksettings = gmac_set_ksettings,
++ .nway_reset = gmac_nway_reset,
++ .get_pauseparam = gmac_get_pauseparam,
++ .get_ringparam = gmac_get_ringparam,
++ .set_ringparam = gmac_set_ringparam,
++ .get_coalesce = gmac_get_coalesce,
++ .set_coalesce = gmac_set_coalesce,
++ .get_msglevel = gmac_get_msglevel,
++ .set_msglevel = gmac_set_msglevel,
++ .get_drvinfo = gmac_get_drvinfo,
++};
++
++static irqreturn_t gemini_port_irq_thread(int irq, void *data)
++{
++ unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
++ struct gemini_ethernet_port *port = data;
++ struct gemini_ethernet *geth;
++ unsigned long flags;
++
++ geth = port->geth;
++ /* The queue is half empty so refill it */
++ geth_fill_freeq(geth, true);
++
++ spin_lock_irqsave(&geth->irq_lock, flags);
++ /* ACK queue interrupt */
++ writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ /* Enable queue interrupt again */
++ irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t gemini_port_irq(int irq, void *data)
++{
++ struct gemini_ethernet_port *port = data;
++ struct gemini_ethernet *geth;
++ irqreturn_t ret = IRQ_NONE;
++ u32 val, en;
++
++ geth = port->geth;
++ spin_lock(&geth->irq_lock);
++
++ val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++ en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ if (val & en & SWFQ_EMPTY_INT_BIT) {
++ /* Disable the queue empty interrupt while we work on
++ * processing the queue. Also disable overrun interrupts
++ * as there is not much we can do about it here.
++ */
++ en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
++ | GMAC1_RX_OVERRUN_INT_BIT);
++ writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++ ret = IRQ_WAKE_THREAD;
++ }
++
++ spin_unlock(&geth->irq_lock);
++
++ return ret;
++}
++
++static void gemini_port_remove(struct gemini_ethernet_port *port)
++{
++ if (port->netdev)
++ unregister_netdev(port->netdev);
++ clk_disable_unprepare(port->pclk);
++ geth_cleanup_freeq(port->geth);
++}
++
++static void gemini_ethernet_init(struct gemini_ethernet *geth)
++{
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
++ writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
++
++ /* Interrupt config:
++ *
++ * GMAC0 intr bits ------> int0 ----> eth0
++ * GMAC1 intr bits ------> int1 ----> eth1
++ * TOE intr -------------> int1 ----> eth1
++ * Classification Intr --> int0 ----> eth0
++ * Default Q0 -----------> int0 ----> eth0
++ * Default Q1 -----------> int1 ----> eth1
++ * FreeQ intr -----------> int1 ----> eth1
++ */
++ writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
++ writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
++ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
++ writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
++ writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
++
++ /* edge-triggered interrupts packed to level-triggered one... */
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
++ writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
++
++ /* Set up queue */
++ writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
++ writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
++ writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
++ writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
++
++ geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
++ /* This makes the queue resize on probe() so that we
++ * set up and enable the queue IRQ. FIXME: fragile.
++ */
++ geth->freeq_order = 1;
++}
++
++static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
++{
++ port->mac_addr[0] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
++ port->mac_addr[1] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
++ port->mac_addr[2] =
++ cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
++}
++
++static int gemini_ethernet_port_probe(struct platform_device *pdev)
++{
++ char *port_names[2] = { "ethernet0", "ethernet1" };
++ struct gemini_ethernet_port *port;
++ struct device *dev = &pdev->dev;
++ struct gemini_ethernet *geth;
++ struct net_device *netdev;
++ struct resource *gmacres;
++ struct resource *dmares;
++ struct device *parent;
++ unsigned int id;
++ int irq;
++ int ret;
++
++ parent = dev->parent;
++ geth = dev_get_drvdata(parent);
++
++ if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
++ id = 0;
++ else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
++ id = 1;
++ else
++ return -ENODEV;
++
++ dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
++
++ netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
++ if (!netdev) {
++ dev_err(dev, "Can't allocate ethernet device #%d\n", id);
++ return -ENOMEM;
++ }
++
++ port = netdev_priv(netdev);
++ SET_NETDEV_DEV(netdev, dev);
++ port->netdev = netdev;
++ port->id = id;
++ port->geth = geth;
++ port->dev = dev;
++
++ /* DMA memory */
++ dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!dmares) {
++ dev_err(dev, "no DMA resource\n");
++ return -ENODEV;
++ }
++ port->dma_base = devm_ioremap_resource(dev, dmares);
++ if (IS_ERR(port->dma_base))
++ return PTR_ERR(port->dma_base);
++
++ /* GMAC config memory */
++ gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!gmacres) {
++ dev_err(dev, "no GMAC resource\n");
++ return -ENODEV;
++ }
++ port->gmac_base = devm_ioremap_resource(dev, gmacres);
++ if (IS_ERR(port->gmac_base))
++ return PTR_ERR(port->gmac_base);
++
++ /* Interrupt */
++ irq = platform_get_irq(pdev, 0);
++ if (irq <= 0) {
++ dev_err(dev, "no IRQ\n");
++ return irq ? irq : -ENODEV;
++ }
++ port->irq = irq;
++
++ /* Clock the port */
++ port->pclk = devm_clk_get(dev, "PCLK");
++ if (IS_ERR(port->pclk)) {
++ dev_err(dev, "no PCLK\n");
++ return PTR_ERR(port->pclk);
++ }
++ ret = clk_prepare_enable(port->pclk);
++ if (ret)
++ return ret;
++
++ /* Maybe there is a nice ethernet address we should use */
++ gemini_port_save_mac_addr(port);
++
++ /* Reset the port */
++ port->reset = devm_reset_control_get_exclusive(dev, NULL);
++ if (IS_ERR(port->reset)) {
++ dev_err(dev, "no reset\n");
++ return PTR_ERR(port->reset);
++ }
++ reset_control_reset(port->reset);
++ usleep_range(100, 500);
++
++ /* Assign pointer in the main state container */
++ if (!id)
++ geth->port0 = port;
++ else
++ geth->port1 = port;
++ platform_set_drvdata(pdev, port);
++
++ /* Set up and register the netdev */
++ netdev->dev_id = port->id;
++ netdev->irq = irq;
++ netdev->netdev_ops = &gmac_351x_ops;
++ netdev->ethtool_ops = &gmac_351x_ethtool_ops;
++
++ spin_lock_init(&port->config_lock);
++ gmac_clear_hw_stats(netdev);
++
++ netdev->hw_features = GMAC_OFFLOAD_FEATURES;
++ netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
++
++ port->freeq_refill = 0;
++ netif_napi_add(netdev, &port->napi, gmac_napi_poll,
++ DEFAULT_NAPI_WEIGHT);
++
++ if (is_valid_ether_addr((void *)port->mac_addr)) {
++ memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
++ } else {
++ dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
++ port->mac_addr[0], port->mac_addr[1],
++ port->mac_addr[2]);
++ dev_info(dev, "using a random ethernet address\n");
++ random_ether_addr(netdev->dev_addr);
++ }
++ gmac_write_mac_address(netdev);
++
++ ret = devm_request_threaded_irq(port->dev,
++ port->irq,
++ gemini_port_irq,
++ gemini_port_irq_thread,
++ IRQF_SHARED,
++ port_names[port->id],
++ port);
++ if (ret)
++ return ret;
++
++ ret = register_netdev(netdev);
++ if (!ret) {
++ netdev_info(netdev,
++ "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
++ port->irq, &dmares->start,
++ &gmacres->start);
++ ret = gmac_setup_phy(netdev);
++ if (ret)
++ netdev_info(netdev,
++ "PHY init failed, deferring to ifup time\n");
++ return 0;
++ }
++
++ port->netdev = NULL;
++ free_netdev(netdev);
++ return ret;
++}
++
++static int gemini_ethernet_port_remove(struct platform_device *pdev)
++{
++ struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
++
++ gemini_port_remove(port);
++ return 0;
++}
++
++static const struct of_device_id gemini_ethernet_port_of_match[] = {
++ {
++ .compatible = "cortina,gemini-ethernet-port",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
++
++static struct platform_driver gemini_ethernet_port_driver = {
++ .driver = {
++ .name = "gemini-ethernet-port",
++ .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
++ },
++ .probe = gemini_ethernet_port_probe,
++ .remove = gemini_ethernet_port_remove,
++};
++
++static int gemini_ethernet_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct gemini_ethernet *geth;
++ unsigned int retry = 5;
++ struct resource *res;
++ u32 val;
++
++ /* Global registers */
++ geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
++ if (!geth)
++ return -ENOMEM;
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++ geth->base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(geth->base))
++ return PTR_ERR(geth->base);
++ geth->dev = dev;
++
++ /* Wait for ports to stabilize */
++ do {
++ udelay(2);
++ val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
++ barrier();
++ } while (!val && --retry);
++ if (!retry) {
++ dev_err(dev, "failed to reset ethernet\n");
++ return -EIO;
++ }
++ dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
++ (val >> 4) & 0xFFFU, val & 0xFU);
++
++ spin_lock_init(&geth->irq_lock);
++ spin_lock_init(&geth->freeq_lock);
++ gemini_ethernet_init(geth);
++
++ /* The children will use this */
++ platform_set_drvdata(pdev, geth);
++
++ /* Spawn child devices for the two ports */
++ return devm_of_platform_populate(dev);
++}
++
++static int gemini_ethernet_remove(struct platform_device *pdev)
++{
++ struct gemini_ethernet *geth = platform_get_drvdata(pdev);
++
++ gemini_ethernet_init(geth);
++ geth_cleanup_freeq(geth);
++
++ return 0;
++}
++
++static const struct of_device_id gemini_ethernet_of_match[] = {
++ {
++ .compatible = "cortina,gemini-ethernet",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
++
++static struct platform_driver gemini_ethernet_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .of_match_table = of_match_ptr(gemini_ethernet_of_match),
++ },
++ .probe = gemini_ethernet_probe,
++ .remove = gemini_ethernet_remove,
++};
++
++static int __init gemini_ethernet_module_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&gemini_ethernet_port_driver);
++ if (ret)
++ return ret;
++
++ ret = platform_driver_register(&gemini_ethernet_driver);
++ if (ret) {
++ platform_driver_unregister(&gemini_ethernet_port_driver);
++ return ret;
++ }
++
++ return 0;
++}
++module_init(gemini_ethernet_module_init);
++
++static void __exit gemini_ethernet_module_exit(void)
++{
++ platform_driver_unregister(&gemini_ethernet_driver);
++ platform_driver_unregister(&gemini_ethernet_port_driver);
++}
++module_exit(gemini_ethernet_module_exit);
++
++MODULE_AUTHOR("Linus Walleij <***@linaro.org>");
++MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
+--- /dev/null
++++ b/drivers/net/ethernet/cortina/gemini.h
+@@ -0,0 +1,958 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Register definitions for Gemini GMAC Ethernet device driver
++ *
++ * Copyright (C) 2006 Storlink, Corp.
++ * Copyright (C) 2008-2009 Paulius Zaleckas <***@teltonika.lt>
++ * Copyright (C) 2010 Michał Mirosław <mirq-***@rere.qmqm.pl>
++ * Copytight (C) 2017 Linus Walleij <***@linaro.org>
++ */
++#ifndef _GEMINI_ETHERNET_H
++#define _GEMINI_ETHERNET_H
++
++#include <linux/bitops.h>
++
++/* Base Registers */
++#define TOE_NONTOE_QUE_HDR_BASE 0x2000
++#define TOE_TOE_QUE_HDR_BASE 0x3000
++
++/* Queue ID */
++#define TOE_SW_FREE_QID 0x00
++#define TOE_HW_FREE_QID 0x01
++#define TOE_GMAC0_SW_TXQ0_QID 0x02
++#define TOE_GMAC0_SW_TXQ1_QID 0x03
++#define TOE_GMAC0_SW_TXQ2_QID 0x04
++#define TOE_GMAC0_SW_TXQ3_QID 0x05
++#define TOE_GMAC0_SW_TXQ4_QID 0x06
++#define TOE_GMAC0_SW_TXQ5_QID 0x07
++#define TOE_GMAC0_HW_TXQ0_QID 0x08
++#define TOE_GMAC0_HW_TXQ1_QID 0x09
++#define TOE_GMAC0_HW_TXQ2_QID 0x0A
++#define TOE_GMAC0_HW_TXQ3_QID 0x0B
++#define TOE_GMAC1_SW_TXQ0_QID 0x12
++#define TOE_GMAC1_SW_TXQ1_QID 0x13
++#define TOE_GMAC1_SW_TXQ2_QID 0x14
++#define TOE_GMAC1_SW_TXQ3_QID 0x15
++#define TOE_GMAC1_SW_TXQ4_QID 0x16
++#define TOE_GMAC1_SW_TXQ5_QID 0x17
++#define TOE_GMAC1_HW_TXQ0_QID 0x18
++#define TOE_GMAC1_HW_TXQ1_QID 0x19
++#define TOE_GMAC1_HW_TXQ2_QID 0x1A
++#define TOE_GMAC1_HW_TXQ3_QID 0x1B
++#define TOE_GMAC0_DEFAULT_QID 0x20
++#define TOE_GMAC1_DEFAULT_QID 0x21
++#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
++#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
++
++/* TOE DMA Queue Size should be 2^n, n = 6...12
++ * TOE DMA Queues are the following queue types:
++ * SW Free Queue, HW Free Queue,
++ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
++ * The base address and descriptor number are configured at
++ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
++ */
++#define GET_WPTR(addr) readw((addr) + 2)
++#define GET_RPTR(addr) readw((addr))
++#define SET_WPTR(addr, data) writew((data), (addr) + 2)
++#define SET_RPTR(addr, data) writew((data), (addr))
++#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
++#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
++#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
++#define __RWPTR_MASK(order) ((1 << (order)) - 1)
++#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
++#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
++#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
++ __RWPTR_MASK((order)))
++
++/* Global registers */
++#define GLOBAL_TOE_VERSION_REG 0x0000
++#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
++#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
++#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
++#define GLOBAL_SWFQ_RWPTR_REG 0x0014
++#define GLOBAL_HWFQ_RWPTR_REG 0x0018
++#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
++#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
++#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
++#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
++#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
++#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
++#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
++#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
++#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
++#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
++#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
++#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
++#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
++#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
++#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
++#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
++#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
++
++/* GMAC 0/1 DMA/TOE register */
++#define GMAC_DMA_CTRL_REG 0x0000
++#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
++#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
++#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
++#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
++#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
++#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
++#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
++#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
++#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
++#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
++#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
++#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
++#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
++#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
++#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
++#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
++#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
++#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
++#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
++#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
++#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
++#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
++#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
++#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
++#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
++#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
++#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
++#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
++#define GMAC_HASH_ENGINE_REG0 0x0070
++#define GMAC_HASH_ENGINE_REG1 0x0074
++/* matching rule 0 Control register 0 */
++#define GMAC_MR0CR0 0x0078
++#define GMAC_MR0CR1 0x007C
++#define GMAC_MR0CR2 0x0080
++#define GMAC_MR1CR0 0x0084
++#define GMAC_MR1CR1 0x0088
++#define GMAC_MR1CR2 0x008C
++#define GMAC_MR2CR0 0x0090
++#define GMAC_MR2CR1 0x0094
++#define GMAC_MR2CR2 0x0098
++#define GMAC_MR3CR0 0x009C
++#define GMAC_MR3CR1 0x00A0
++#define GMAC_MR3CR2 0x00A4
++/* Support Protocol Register 0 */
++#define GMAC_SPR0 0x00A8
++#define GMAC_SPR1 0x00AC
++#define GMAC_SPR2 0x00B0
++#define GMAC_SPR3 0x00B4
++#define GMAC_SPR4 0x00B8
++#define GMAC_SPR5 0x00BC
++#define GMAC_SPR6 0x00C0
++#define GMAC_SPR7 0x00C4
++/* GMAC Hash/Rx/Tx AHB Weighting register */
++#define GMAC_AHB_WEIGHT_REG 0x00C8
++
++/* TOE GMAC 0/1 register */
++#define GMAC_STA_ADD0 0x0000
++#define GMAC_STA_ADD1 0x0004
++#define GMAC_STA_ADD2 0x0008
++#define GMAC_RX_FLTR 0x000c
++#define GMAC_MCAST_FIL0 0x0010
++#define GMAC_MCAST_FIL1 0x0014
++#define GMAC_CONFIG0 0x0018
++#define GMAC_CONFIG1 0x001c
++#define GMAC_CONFIG2 0x0020
++#define GMAC_CONFIG3 0x0024
++#define GMAC_RESERVED 0x0028
++#define GMAC_STATUS 0x002c
++#define GMAC_IN_DISCARDS 0x0030
++#define GMAC_IN_ERRORS 0x0034
++#define GMAC_IN_MCAST 0x0038
++#define GMAC_IN_BCAST 0x003c
++#define GMAC_IN_MAC1 0x0040 /* for STA 1 MAC Address */
++#define GMAC_IN_MAC2 0x0044 /* for STA 2 MAC Address */
++
++#define RX_STATS_NUM 6
++
++/* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
++union dma_q_base_size {
++ unsigned int bits32;
++ unsigned int base_size;
++};
++
++#define DMA_Q_BASE_MASK (~0x0f)
++
++/* DMA SKB Buffer register (offset 0x0008) */
++union dma_skb_size {
++ unsigned int bits32;
++ struct bit_0008 {
++ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
++ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
++ } bits;
++};
++
++/* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
++union dma_rwptr {
++ unsigned int bits32;
++ struct bit_000c {
++ unsigned int rptr : 16; /* Read Ptr, RO */
++ unsigned int wptr : 16; /* Write Ptr, RW */
++ } bits;
++};
++
++/* Interrupt Status Register 0 (offset 0x0020)
++ * Interrupt Mask Register 0 (offset 0x0024)
++ * Interrupt Select Register 0 (offset 0x0028)
++ */
++#define GMAC1_TXDERR_INT_BIT BIT(31)
++#define GMAC1_TXPERR_INT_BIT BIT(30)
++#define GMAC0_TXDERR_INT_BIT BIT(29)
++#define GMAC0_TXPERR_INT_BIT BIT(28)
++#define GMAC1_RXDERR_INT_BIT BIT(27)
++#define GMAC1_RXPERR_INT_BIT BIT(26)
++#define GMAC0_RXDERR_INT_BIT BIT(25)
++#define GMAC0_RXPERR_INT_BIT BIT(24)
++#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
++#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
++#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
++#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
++#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
++#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
++#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
++#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
++#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
++#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
++#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
++#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
++#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
++#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
++#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
++#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
++#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
++#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
++#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
++#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
++#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
++#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
++#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
++#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
++
++/* Interrupt Status Register 1 (offset 0x0030)
++ * Interrupt Mask Register 1 (offset 0x0034)
++ * Interrupt Select Register 1 (offset 0x0038)
++ */
++#define TOE_IQ3_FULL_INT_BIT BIT(31)
++#define TOE_IQ2_FULL_INT_BIT BIT(30)
++#define TOE_IQ1_FULL_INT_BIT BIT(29)
++#define TOE_IQ0_FULL_INT_BIT BIT(28)
++#define TOE_IQ3_INT_BIT BIT(27)
++#define TOE_IQ2_INT_BIT BIT(26)
++#define TOE_IQ1_INT_BIT BIT(25)
++#define TOE_IQ0_INT_BIT BIT(24)
++#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
++#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
++#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
++#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
++#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
++#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
++#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
++#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
++#define CLASS_RX_INT_BIT(x) BIT((x + 2))
++#define DEFAULT_Q1_INT_BIT BIT(1)
++#define DEFAULT_Q0_INT_BIT BIT(0)
++
++#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
++ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
++#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
++ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
++#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
++#define TOE_CLASS_RX_INT_BITS 0xfffc
++
++/* Interrupt Status Register 2 (offset 0x0040)
++ * Interrupt Mask Register 2 (offset 0x0044)
++ * Interrupt Select Register 2 (offset 0x0048)
++ */
++#define TOE_QL_FULL_INT_BIT(x) BIT(x)
++
++/* Interrupt Status Register 3 (offset 0x0050)
++ * Interrupt Mask Register 3 (offset 0x0054)
++ * Interrupt Select Register 3 (offset 0x0058)
++ */
++#define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
++
++/* Interrupt Status Register 4 (offset 0x0060)
++ * Interrupt Mask Register 4 (offset 0x0064)
++ * Interrupt Select Register 4 (offset 0x0068)
++ */
++#define GMAC1_RESERVED_INT_BIT BIT(31)
++#define GMAC1_MIB_INT_BIT BIT(30)
++#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
++#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
++#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
++#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
++#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
++#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
++#define GMAC0_RESERVED_INT_BIT BIT(23)
++#define GMAC0_MIB_INT_BIT BIT(22)
++#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
++#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
++#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
++#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
++#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
++#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
++#define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2)
++#define HWFQ_EMPTY_INT_BIT BIT(1)
++#define SWFQ_EMPTY_INT_BIT BIT(0)
++
++#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
++ GMAC0_RX_PAUSE_ON_INT_BIT | \
++ GMAC0_TX_PAUSE_ON_INT_BIT | \
++ GMAC0_RX_PAUSE_OFF_INT_BIT | \
++ GMAC0_TX_PAUSE_OFF_INT_BIT | \
++ GMAC0_RX_OVERRUN_INT_BIT | \
++ GMAC0_STATUS_CHANGE_INT_BIT)
++#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
++ GMAC1_RX_PAUSE_ON_INT_BIT | \
++ GMAC1_TX_PAUSE_ON_INT_BIT | \
++ GMAC1_RX_PAUSE_OFF_INT_BIT | \
++ GMAC1_TX_PAUSE_OFF_INT_BIT | \
++ GMAC1_RX_OVERRUN_INT_BIT | \
++ GMAC1_STATUS_CHANGE_INT_BIT)
++
++#define CLASS_RX_FULL_INT_BITS 0xfffc
++
++/* GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) */
++union queue_threshold {
++ unsigned int bits32;
++ struct bit_0070_2 {
++ /* 7:0 Software Free Queue Empty Threshold */
++ unsigned int swfq_empty:8;
++ /* 15:8 Hardware Free Queue Empty Threshold */
++ unsigned int hwfq_empty:8;
++ /* 23:16 */
++ unsigned int intrq:8;
++ /* 31:24 */
++ unsigned int toe_class:8;
++ } bits;
++};
++
++/* GMAC DMA Control Register
++ * GMAC0 offset 0x8000
++ * GMAC1 offset 0xC000
++ */
++union gmac_dma_ctrl {
++ unsigned int bits32;
++ struct bit_8000 {
++ /* bit 1:0 Peripheral Bus Width */
++ unsigned int td_bus:2;
++ /* bit 3:2 TxDMA max burst size for every AHB request */
++ unsigned int td_burst_size:2;
++ /* bit 7:4 TxDMA protection control */
++ unsigned int td_prot:4;
++ /* bit 9:8 Peripheral Bus Width */
++ unsigned int rd_bus:2;
++ /* bit 11:10 DMA max burst size for every AHB request */
++ unsigned int rd_burst_size:2;
++ /* bit 15:12 DMA Protection Control */
++ unsigned int rd_prot:4;
++ /* bit 17:16 */
++ unsigned int rd_insert_bytes:2;
++ /* bit 27:18 */
++ unsigned int reserved:10;
++ /* bit 28 1: Drop, 0: Accept */
++ unsigned int drop_small_ack:1;
++ /* bit 29 Loopback TxDMA to RxDMA */
++ unsigned int loopback:1;
++ /* bit 30 Tx DMA Enable */
++ unsigned int td_enable:1;
++ /* bit 31 Rx DMA Enable */
++ unsigned int rd_enable:1;
++ } bits;
++};
++
++/* GMAC Tx Weighting Control Register 0
++ * GMAC0 offset 0x8004
++ * GMAC1 offset 0xC004
++ */
++union gmac_tx_wcr0 {
++ unsigned int bits32;
++ struct bit_8004 {
++ /* bit 5:0 HW TX Queue 3 */
++ unsigned int hw_tq0:6;
++ /* bit 11:6 HW TX Queue 2 */
++ unsigned int hw_tq1:6;
++ /* bit 17:12 HW TX Queue 1 */
++ unsigned int hw_tq2:6;
++ /* bit 23:18 HW TX Queue 0 */
++ unsigned int hw_tq3:6;
++ /* bit 31:24 */
++ unsigned int reserved:8;
++ } bits;
++};
++
++/* GMAC Tx Weighting Control Register 1
++ * GMAC0 offset 0x8008
++ * GMAC1 offset 0xC008
++ */
++union gmac_tx_wcr1 {
++ unsigned int bits32;
++ struct bit_8008 {
++ /* bit 4:0 SW TX Queue 0 */
++ unsigned int sw_tq0:5;
++ /* bit 9:5 SW TX Queue 1 */
++ unsigned int sw_tq1:5;
++ /* bit 14:10 SW TX Queue 2 */
++ unsigned int sw_tq2:5;
++ /* bit 19:15 SW TX Queue 3 */
++ unsigned int sw_tq3:5;
++ /* bit 24:20 SW TX Queue 4 */
++ unsigned int sw_tq4:5;
++ /* bit 29:25 SW TX Queue 5 */
++ unsigned int sw_tq5:5;
++ /* bit 31:30 */
++ unsigned int reserved:2;
++ } bits;
++};
++
++/* GMAC DMA Tx Description Word 0 Register
++ * GMAC0 offset 0x8040
++ * GMAC1 offset 0xC040
++ */
++union gmac_txdesc_0 {
++ unsigned int bits32;
++ struct bit_8040 {
++ /* bit 15:0 Transfer size */
++ unsigned int buffer_size:16;
++ /* bit 21:16 number of descriptors used for the current frame */
++ unsigned int desc_count:6;
++ /* bit 22 Tx Status, 1: Successful 0: Failed */
++ unsigned int status_tx_ok:1;
++ /* bit 28:23 Tx Status, Reserved bits */
++ unsigned int status_rvd:6;
++ /* bit 29 protocol error during processing this descriptor */
++ unsigned int perr:1;
++ /* bit 30 data error during processing this descriptor */
++ unsigned int derr:1;
++ /* bit 31 */
++ unsigned int reserved:1;
++ } bits;
++};
++
++/* GMAC DMA Tx Description Word 1 Register
++ * GMAC0 offset 0x8044
++ * GMAC1 offset 0xC044
++ */
++union gmac_txdesc_1 {
++ unsigned int bits32;
++ struct txdesc_word1 {
++ /* bit 15: 0 Tx Frame Byte Count */
++ unsigned int byte_count:16;
++ /* bit 16 TSS segmentation use MTU setting */
++ unsigned int mtu_enable:1;
++ /* bit 17 IPV4 Header Checksum Enable */
++ unsigned int ip_chksum:1;
++ /* bit 18 IPV6 Tx Enable */
++ unsigned int ipv6_enable:1;
++ /* bit 19 TCP Checksum Enable */
++ unsigned int tcp_chksum:1;
++ /* bit 20 UDP Checksum Enable */
++ unsigned int udp_chksum:1;
++ /* bit 21 Bypass HW offload engine */
++ unsigned int bypass_tss:1;
++ /* bit 22 Don't update IP length field */
++ unsigned int ip_fixed_len:1;
++ /* bit 31:23 Tx Flag, Reserved */
++ unsigned int reserved:9;
++ } bits;
++};
++
++#define TSS_IP_FIXED_LEN_BIT BIT(22)
++#define TSS_BYPASS_BIT BIT(21)
++#define TSS_UDP_CHKSUM_BIT BIT(20)
++#define TSS_TCP_CHKSUM_BIT BIT(19)
++#define TSS_IPV6_ENABLE_BIT BIT(18)
++#define TSS_IP_CHKSUM_BIT BIT(17)
++#define TSS_MTU_ENABLE_BIT BIT(16)
++
++#define TSS_CHECKUM_ENABLE \
++ (TSS_IP_CHKSUM_BIT | TSS_IPV6_ENABLE_BIT | \
++ TSS_TCP_CHKSUM_BIT | TSS_UDP_CHKSUM_BIT)
++
++/* GMAC DMA Tx Description Word 2 Register
++ * GMAC0 offset 0x8048
++ * GMAC1 offset 0xC048
++ */
++union gmac_txdesc_2 {
++ unsigned int bits32;
++ unsigned int buf_adr;
++};
++
++/* GMAC DMA Tx Description Word 3 Register
++ * GMAC0 offset 0x804C
++ * GMAC1 offset 0xC04C
++ */
++union gmac_txdesc_3 {
++ unsigned int bits32;
++ struct txdesc_word3 {
++ /* bit 12: 0 Tx Frame Byte Count */
++ unsigned int mtu_size:13;
++ /* bit 28:13 */
++ unsigned int reserved:16;
++ /* bit 29 End of frame interrupt enable */
++ unsigned int eofie:1;
++ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
++ unsigned int sof_eof:2;
++ } bits;
++};
++
++#define SOF_EOF_BIT_MASK 0x3fffffff
++#define SOF_BIT 0x80000000
++#define EOF_BIT 0x40000000
++#define EOFIE_BIT BIT(29)
++#define MTU_SIZE_BIT_MASK 0x1fff
++
++/* GMAC Tx Descriptor */
++struct gmac_txdesc {
++ union gmac_txdesc_0 word0;
++ union gmac_txdesc_1 word1;
++ union gmac_txdesc_2 word2;
++ union gmac_txdesc_3 word3;
++};
++
++/* GMAC DMA Rx Description Word 0 Register
++ * GMAC0 offset 0x8060
++ * GMAC1 offset 0xC060
++ */
++union gmac_rxdesc_0 {
++ unsigned int bits32;
++ struct bit_8060 {
++ /* bit 15:0 number of descriptors used for the current frame */
++ unsigned int buffer_size:16;
++ /* bit 21:16 number of descriptors used for the current frame */
++ unsigned int desc_count:6;
++ /* bit 24:22 Status of rx frame */
++ unsigned int status:4;
++ /* bit 28:26 Check Sum Status */
++ unsigned int chksum_status:3;
++ /* bit 29 protocol error during processing this descriptor */
++ unsigned int perr:1;
++ /* bit 30 data error during processing this descriptor */
++ unsigned int derr:1;
++ /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
++ unsigned int drop:1;
++ } bits;
++};
++
++#define GMAC_RXDESC_0_T_derr BIT(30)
++#define GMAC_RXDESC_0_T_perr BIT(29)
++#define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26)
++#define GMAC_RXDESC_0_T_status(x) BIT(x + 22)
++#define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16)
++
++#define RX_CHKSUM_IP_UDP_TCP_OK 0
++#define RX_CHKSUM_IP_OK_ONLY 1
++#define RX_CHKSUM_NONE 2
++#define RX_CHKSUM_IP_ERR_UNKNOWN 4
++#define RX_CHKSUM_IP_ERR 5
++#define RX_CHKSUM_TCP_UDP_ERR 6
++#define RX_CHKSUM_NUM 8
++
++#define RX_STATUS_GOOD_FRAME 0
++#define RX_STATUS_TOO_LONG_GOOD_CRC 1
++#define RX_STATUS_RUNT_FRAME 2
++#define RX_STATUS_SFD_NOT_FOUND 3
++#define RX_STATUS_CRC_ERROR 4
++#define RX_STATUS_TOO_LONG_BAD_CRC 5
++#define RX_STATUS_ALIGNMENT_ERROR 6
++#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
++#define RX_STATUS_RX_ERR 8
++#define RX_STATUS_DA_FILTERED 9
++#define RX_STATUS_BUFFER_FULL 10
++#define RX_STATUS_NUM 16
++
++#define RX_ERROR_LENGTH(s) \
++ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
++ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
++#define RX_ERROR_OVER(s) \
++ ((s) == RX_STATUS_BUFFER_FULL)
++#define RX_ERROR_CRC(s) \
++ ((s) == RX_STATUS_CRC_ERROR || \
++ (s) == RX_STATUS_TOO_LONG_BAD_CRC)
++#define RX_ERROR_FRAME(s) \
++ ((s) == RX_STATUS_ALIGNMENT_ERROR || \
++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
++#define RX_ERROR_FIFO(s) \
++ (0)
++
++/* GMAC DMA Rx Description Word 1 Register
++ * GMAC0 offset 0x8064
++ * GMAC1 offset 0xC064
++ */
++union gmac_rxdesc_1 {
++ unsigned int bits32;
++ struct rxdesc_word1 {
++ /* bit 15: 0 Rx Frame Byte Count */
++ unsigned int byte_count:16;
++ /* bit 31:16 Software ID */
++ unsigned int sw_id:16;
++ } bits;
++};
++
++/* GMAC DMA Rx Description Word 2 Register
++ * GMAC0 offset 0x8068
++ * GMAC1 offset 0xC068
++ */
++union gmac_rxdesc_2 {
++ unsigned int bits32;
++ unsigned int buf_adr;
++};
++
++#define RX_INSERT_NONE 0
++#define RX_INSERT_1_BYTE 1
++#define RX_INSERT_2_BYTE 2
++#define RX_INSERT_3_BYTE 3
++
++/* GMAC DMA Rx Description Word 3 Register
++ * GMAC0 offset 0x806C
++ * GMAC1 offset 0xC06C
++ */
++union gmac_rxdesc_3 {
++ unsigned int bits32;
++ struct rxdesc_word3 {
++ /* bit 7: 0 L3 data offset */
++ unsigned int l3_offset:8;
++ /* bit 15: 8 L4 data offset */
++ unsigned int l4_offset:8;
++ /* bit 23: 16 L7 data offset */
++ unsigned int l7_offset:8;
++ /* bit 24 Duplicated ACK detected */
++ unsigned int dup_ack:1;
++ /* bit 25 abnormal case found */
++ unsigned int abnormal:1;
++ /* bit 26 IPV4 option or IPV6 extension header */
++ unsigned int option:1;
++ /* bit 27 Out of Sequence packet */
++ unsigned int out_of_seq:1;
++ /* bit 28 Control Flag is present */
++ unsigned int ctrl_flag:1;
++ /* bit 29 End of frame interrupt enable */
++ unsigned int eofie:1;
++ /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
++ unsigned int sof_eof:2;
++ } bits;
++};
++
++/* GMAC Rx Descriptor, this is simply fitted over the queue registers */
++struct gmac_rxdesc {
++ union gmac_rxdesc_0 word0;
++ union gmac_rxdesc_1 word1;
++ union gmac_rxdesc_2 word2;
++ union gmac_rxdesc_3 word3;
++};
++
++/* GMAC Matching Rule Control Register 0
++ * GMAC0 offset 0x8078
++ * GMAC1 offset 0xC078
++ */
++#define MR_L2_BIT BIT(31)
++#define MR_L3_BIT BIT(30)
++#define MR_L4_BIT BIT(29)
++#define MR_L7_BIT BIT(28)
++#define MR_PORT_BIT BIT(27)
++#define MR_PRIORITY_BIT BIT(26)
++#define MR_DA_BIT BIT(23)
++#define MR_SA_BIT BIT(22)
++#define MR_ETHER_TYPE_BIT BIT(21)
++#define MR_VLAN_BIT BIT(20)
++#define MR_PPPOE_BIT BIT(19)
++#define MR_IP_VER_BIT BIT(15)
++#define MR_IP_HDR_LEN_BIT BIT(14)
++#define MR_FLOW_LABLE_BIT BIT(13)
++#define MR_TOS_TRAFFIC_BIT BIT(12)
++#define MR_SPR_BIT(x) BIT(x)
++#define MR_SPR_BITS 0xff
++
++/* GMAC_AHB_WEIGHT registers
++ * GMAC0 offset 0x80C8
++ * GMAC1 offset 0xC0C8
++ */
++union gmac_ahb_weight {
++ unsigned int bits32;
++ struct bit_80C8 {
++ /* 4:0 */
++ unsigned int hash_weight:5;
++ /* 9:5 */
++ unsigned int rx_weight:5;
++ /* 14:10 */
++ unsigned int tx_weight:5;
++ /* 19:15 Rx Data Pre Request FIFO Threshold */
++ unsigned int pre_req:5;
++ /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
++ unsigned int tq_dv_threshold:5;
++ /* 31:25 */
++ unsigned int reserved:7;
++ } bits;
++};
++
++/* GMAC RX FLTR
++ * GMAC0 Offset 0xA00C
++ * GMAC1 Offset 0xE00C
++ */
++union gmac_rx_fltr {
++ unsigned int bits32;
++ struct bit1_000c {
++ /* Enable receive of unicast frames that are sent to STA
++ * address
++ */
++ unsigned int unicast:1;
++ /* Enable receive of multicast frames that pass multicast
++ * filter
++ */
++ unsigned int multicast:1;
++ /* Enable receive of broadcast frames */
++ unsigned int broadcast:1;
++ /* Enable receive of all frames */
++ unsigned int promiscuous:1;
++ /* Enable receive of all error frames */
++ unsigned int error:1;
++ unsigned int reserved:27;
++ } bits;
++};
++
++/* GMAC Configuration 0
++ * GMAC0 Offset 0xA018
++ * GMAC1 Offset 0xE018
++ */
++union gmac_config0 {
++ unsigned int bits32;
++ struct bit1_0018 {
++ /* 0: disable transmit */
++ unsigned int dis_tx:1;
++ /* 1: disable receive */
++ unsigned int dis_rx:1;
++ /* 2: transmit data loopback enable */
++ unsigned int loop_back:1;
++ /* 3: flow control also trigged by Rx queues */
++ unsigned int flow_ctrl:1;
++ /* 4-7: adjust IFG from 96+/-56 */
++ unsigned int adj_ifg:4;
++ /* 8-10 maximum receive frame length allowed */
++ unsigned int max_len:3;
++ /* 11: disable back-off function */
++ unsigned int dis_bkoff:1;
++ /* 12: disable 16 collisions abort function */
++ unsigned int dis_col:1;
++ /* 13: speed up timers in simulation */
++ unsigned int sim_test:1;
++ /* 14: RX flow control enable */
++ unsigned int rx_fc_en:1;
++ /* 15: TX flow control enable */
++ unsigned int tx_fc_en:1;
++ /* 16: RGMII in-band status enable */
++ unsigned int rgmii_en:1;
++ /* 17: IPv4 RX Checksum enable */
++ unsigned int ipv4_rx_chksum:1;
++ /* 18: IPv6 RX Checksum enable */
++ unsigned int ipv6_rx_chksum:1;
++ /* 19: Remove Rx VLAN tag */
++ unsigned int rx_tag_remove:1;
++ /* 20 */
++ unsigned int rgmm_edge:1;
++ /* 21 */
++ unsigned int rxc_inv:1;
++ /* 22 */
++ unsigned int ipv6_exthdr_order:1;
++ /* 23 */
++ unsigned int rx_err_detect:1;
++ /* 24 */
++ unsigned int port0_chk_hwq:1;
++ /* 25 */
++ unsigned int port1_chk_hwq:1;
++ /* 26 */
++ unsigned int port0_chk_toeq:1;
++ /* 27 */
++ unsigned int port1_chk_toeq:1;
++ /* 28 */
++ unsigned int port0_chk_classq:1;
++ /* 29 */
++ unsigned int port1_chk_classq:1;
++ /* 30, 31 */
++ unsigned int reserved:2;
++ } bits;
++};
++
++#define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0))
++#define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17))
++#define CONFIG0_FLOW_RX BIT(14)
++#define CONFIG0_FLOW_TX BIT(15)
++#define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15))
++#define CONFIG0_FLOW_CTL (BIT(14) | BIT(15))
++
++#define CONFIG0_MAXLEN_SHIFT 8
++#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
++#define CONFIG0_MAXLEN_1536 0
++#define CONFIG0_MAXLEN_1518 1
++#define CONFIG0_MAXLEN_1522 2
++#define CONFIG0_MAXLEN_1542 3
++#define CONFIG0_MAXLEN_9k 4 /* 9212 */
++#define CONFIG0_MAXLEN_10k 5 /* 10236 */
++#define CONFIG0_MAXLEN_1518__6 6
++#define CONFIG0_MAXLEN_1518__7 7
++
++/* GMAC Configuration 1
++ * GMAC0 Offset 0xA01C
++ * GMAC1 Offset 0xE01C
++ */
++union gmac_config1 {
++ unsigned int bits32;
++ struct bit1_001c {
++ /* Flow control set threshold */
++ unsigned int set_threshold:8;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:8;
++ unsigned int reserved:16;
++ } bits;
++};
++
++#define GMAC_FLOWCTRL_SET_MAX 32
++#define GMAC_FLOWCTRL_SET_MIN 0
++#define GMAC_FLOWCTRL_RELEASE_MAX 32
++#define GMAC_FLOWCTRL_RELEASE_MIN 0
++
++/* GMAC Configuration 2
++ * GMAC0 Offset 0xA020
++ * GMAC1 Offset 0xE020
++ */
++union gmac_config2 {
++ unsigned int bits32;
++ struct bit1_0020 {
++ /* Flow control set threshold */
++ unsigned int set_threshold:16;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:16;
++ } bits;
++};
++
++/* GMAC Configuration 3
++ * GMAC0 Offset 0xA024
++ * GMAC1 Offset 0xE024
++ */
++union gmac_config3 {
++ unsigned int bits32;
++ struct bit1_0024 {
++ /* Flow control set threshold */
++ unsigned int set_threshold:16;
++ /* Flow control release threshold */
++ unsigned int rel_threshold:16;
++ } bits;
++};
++
++/* GMAC STATUS
++ * GMAC0 Offset 0xA02C
++ * GMAC1 Offset 0xE02C
++ */
++union gmac_status {
++ unsigned int bits32;
++ struct bit1_002c {
++ /* Link status */
++ unsigned int link:1;
++ /* Link speed(00->2.5M 01->25M 10->125M) */
++ unsigned int speed:2;
++ /* Duplex mode */
++ unsigned int duplex:1;
++ unsigned int reserved_1:1;
++ /* PHY interface type */
++ unsigned int mii_rmii:2;
++ unsigned int reserved_2:25;
++ } bits;
++};
++
++#define GMAC_SPEED_10 0
++#define GMAC_SPEED_100 1
++#define GMAC_SPEED_1000 2
++
++#define GMAC_PHY_MII 0
++#define GMAC_PHY_GMII 1
++#define GMAC_PHY_RGMII_100_10 2
++#define GMAC_PHY_RGMII_1000 3
++
++/* Queue Header
++ * (1) TOE Queue Header
++ * (2) Non-TOE Queue Header
++ * (3) Interrupt Queue Header
++ *
++ * memory Layout
++ * TOE Queue Header
++ * 0x60003000 +---------------------------+ 0x0000
++ * | TOE Queue 0 Header |
++ * | 8 * 4 Bytes |
++ * +---------------------------+ 0x0020
++ * | TOE Queue 1 Header |
++ * | 8 * 4 Bytes |
++ * +---------------------------+ 0x0040
++ * | ...... |
++ * | |
++ * +---------------------------+
++ *
++ * Non TOE Queue Header
++ * 0x60002000 +---------------------------+ 0x0000
++ * | Default Queue 0 Header |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x0008
++ * | Default Queue 1 Header |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x0010
++ * | Classification Queue 0 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Classification Queue 1 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ (n * 8 + 0x10)
++ * | ... |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ (13 * 8 + 0x10)
++ * | Classification Queue 13 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+ 0x80
++ * | Interrupt Queue 0 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 1 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 2 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ * | Interrupt Queue 3 |
++ * | 2 * 4 Bytes |
++ * +---------------------------+
++ *
++ */
++#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
++#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
++#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
++#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
++#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
++#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
++#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
++
++/* NONTOE Queue Header Word 0 */
++union nontoe_qhdr0 {
++ unsigned int bits32;
++ unsigned int base_size;
++};
++
++#define NONTOE_QHDR0_BASE_MASK (~0x0f)
++
++/* NONTOE Queue Header Word 1 */
++union nontoe_qhdr1 {
++ unsigned int bits32;
++ struct bit_nonqhdr1 {
++ /* bit 15:0 */
++ unsigned int rptr:16;
++ /* bit 31:16 */
++ unsigned int wptr:16;
++ } bits;
++};
++
++/* Non-TOE Queue Header */
++struct nontoe_qhdr {
++ union nontoe_qhdr0 word0;
++ union nontoe_qhdr1 word1;
++};
++
++#endif /* _GEMINI_ETHERNET_H */
diff --git a/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch b/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch
new file mode 100644
index 000000000000..0960f6bfddaf
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch
@@ -0,0 +1,74 @@
+From 860005c1a2f16aaa33458a7d80c9728b710ae292 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Mon, 6 Nov 2017 00:05:28 +0100
+Subject: [PATCH 23/31] ARM: dts: Add ethernet to the Gemini SoC
+
+This adds the Gemini ethernet node to the Gemini SoC.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ arch/arm/boot/dts/gemini.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 43 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -114,9 +114,16 @@
+ };
+ };
+ gmii_default_pins: pinctrl-gmii {
++ /*
++ * Only activate GMAC0 by default since
++ * GMAC1 will overlap with 8 GPIO lines
++ * gpio2a, gpio2b. Overlay groups with
++ * "gmii_gmac0_grp", "gmii_gmac1_grp" for
++ * both ethernet interfaces.
++ */
+ mux {
+ function = "gmii";
+- groups = "gmiigrp";
++ groups = "gmii_gmac0_grp";
+ };
+ };
+ pci_default_pins: pinctrl-pci {
+@@ -316,6 +323,41 @@
+ };
+ };
+
++ ***@60000000 {
++ compatible = "cortina,gemini-ethernet";
++ reg = <0x60000000 0x4000>, /* Global registers, queue */
++ <0x60004000 0x2000>, /* V-bit */
++ <0x60006000 0x2000>; /* A-bit */
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmii_default_pins>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ gmac0: ethernet-***@0 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
++ <0x6000a000 0x2000>; /* Port 0 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC0>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
++ clock-names = "PCLK";
++ };
++
++ gmac1: ethernet-***@1 {
++ compatible = "cortina,gemini-ethernet-port";
++ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
++ <0x6000e000 0x2000>; /* Port 1 GMAC */
++ interrupt-parent = <&intcon>;
++ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_GMAC1>;
++ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
++ clock-names = "PCLK";
++ };
++ };
++
+ ***@63000000 {
+ compatible = "cortina,gemini-pata", "faraday,ftide010";
+ reg = <0x63000000 0x1000>;
diff --git a/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch b/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch
new file mode 100644
index 000000000000..2b95a9287f79
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0024-net-gemini-Depend-on-HAS_IOMEM.patch
@@ -0,0 +1,30 @@
+From e0a7c7762e3a81e908bcca4176139ea9755d0985 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Sun, 21 Jan 2018 14:15:41 +0100
+Subject: [PATCH 24/31] net: gemini: Depend on HAS_IOMEM
+
+The zeroday builder notices that since Usermode Linux does not
+have IO memory, the build fails for them when selecting everything
+it can enable.
+
+As the driver is clearly using memory-mapped registers to access
+the network adapter, we add depends on HAS_IOMEM to solve this
+problem.
+
+Reported-by: kbuild test robot <***@intel.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+Signed-off-by: David S. Miller <***@davemloft.net>
+---
+ drivers/net/ethernet/cortina/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/cortina/Kconfig
++++ b/drivers/net/ethernet/cortina/Kconfig
+@@ -14,6 +14,7 @@ if NET_VENDOR_CORTINA
+ config GEMINI_ETHERNET
+ tristate "Gemini Gigabit Ethernet support"
+ depends on OF
++ depends on HAS_IOMEM
+ select PHYLIB
+ select CRC32
+ ---help---
diff --git a/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch b/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch
new file mode 100644
index 000000000000..06609a7ed6a6
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch
@@ -0,0 +1,36 @@
+From f30cc6acdeb834be1a6ae54d47c84b2f8012b83d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Thu, 18 Jan 2018 14:36:21 +0100
+Subject: [PATCH 25/31] ARM: dts: Set D-Link DNS-313 SATA to muxmode 0
+
+This stops the driver from trying to probe the ATA slave
+interface. The vendor code enables the slave interface
+but the driver in the vendor tree does not make use of
+it.
+
+Setting it to muxmode 0 disables the slave interface:
+the hardware only has the master interface connected
+to the one harddrive slot anyways.
+
+Without this change booting takes excessive time, so it
+is very annoying to end users.
+
+Fixes: dd5c0561db75 ("ARM: dts: Add basic devicetree for D-Link DNS-313")
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ARM SoC folks: please apply this for fixes for v4.16.
+---
+ arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+@@ -219,7 +219,7 @@
+
+ sata: ***@46000000 {
+ /* The ROM uses this muxmode */
+- cortina,gemini-ata-muxmode = <3>;
++ cortina,gemini-ata-muxmode = <0>;
+ cortina,gemini-enable-sata-bridge;
+ status = "okay";
+ };
diff --git a/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch b/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch
new file mode 100644
index 000000000000..e97aeaca43b2
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch
@@ -0,0 +1,80 @@
+From da443bc125265cae24a0e5f7d1c7bba196a9319f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Thu, 22 Feb 2018 08:34:35 +0100
+Subject: [PATCH 26/31] power: gemini-poweroff: Avoid spurious poweroff
+
+On the D-Link DIR-685 we get spurious poweroff from
+infrared. Since that block (CIR) doesn't even have a
+driver this can be safely ignored, we can revisit this
+code once we have a device supporting CIR.
+
+On the D-Link DNS-313 we get spurious poweroff from
+the power button. This appears to be an initialization
+issue: we need to enable the block (start the state
+machine) before we clear any dangling IRQ.
+
+This patch fixes both issues.
+
+Fixes: f7a388d6cd1c ("power: reset: Add a driver for the Gemini poweroff")
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ChangeLog v1->v2:
+- Fix both issues and rename the patch.
+- Proper commit message with specifics.
+---
+ drivers/power/reset/gemini-poweroff.c | 30 +++++++++++++++++-------------
+ 1 file changed, 17 insertions(+), 13 deletions(-)
+
+--- a/drivers/power/reset/gemini-poweroff.c
++++ b/drivers/power/reset/gemini-poweroff.c
+@@ -47,8 +47,12 @@ static irqreturn_t gemini_powerbutton_in
+ val &= 0x70U;
+ switch (val) {
+ case GEMINI_STAT_CIR:
+- dev_info(gpw->dev, "infrared poweroff\n");
+- orderly_poweroff(true);
++ /*
++ * We do not yet have a driver for the infrared
++ * controller so it can cause spurious poweroff
++ * events. Ignore those for now.
++ */
++ dev_info(gpw->dev, "infrared poweroff - ignored\n");
+ break;
+ case GEMINI_STAT_RTC:
+ dev_info(gpw->dev, "RTC poweroff\n");
+@@ -116,7 +120,17 @@ static int gemini_poweroff_probe(struct
+ return -ENODEV;
+ }
+
+- /* Clear the power management IRQ */
++ /*
++ * Enable the power controller. This is crucial on Gemini
++ * systems: if this is not done, pressing the power button
++ * will result in unconditional poweroff without any warning.
++ * This makes the kernel handle the poweroff.
++ */
++ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
++ val |= GEMINI_CTRL_ENABLE;
++ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
++
++ /* Now that the state machine is active, clear the IRQ */
+ val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+ val |= GEMINI_CTRL_IRQ_CLR;
+ writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+@@ -129,16 +143,6 @@ static int gemini_poweroff_probe(struct
+ pm_power_off = gemini_poweroff;
+ gpw_poweroff = gpw;
+
+- /*
+- * Enable the power controller. This is crucial on Gemini
+- * systems: if this is not done, pressing the power button
+- * will result in unconditional poweroff without any warning.
+- * This makes the kernel handle the poweroff.
+- */
+- val = readl(gpw->base + GEMINI_PWC_CTRLREG);
+- val |= GEMINI_CTRL_ENABLE;
+- writel(val, gpw->base + GEMINI_PWC_CTRLREG);
+-
+ dev_info(dev, "Gemini poweroff driver registered\n");
+
+ return 0;
diff --git a/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch b/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch
new file mode 100644
index 000000000000..e677c3843806
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0027-usb-host-add-DT-bindings-for-faraday-fotg2.patch
@@ -0,0 +1,65 @@
+From 3699f119ff8da021fe7a1759e98e38ca88fa6766 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <***@googlemail.com>
+Date: Wed, 8 Feb 2017 21:00:09 +0100
+Subject: [PATCH 27/31] usb: host: add DT bindings for faraday fotg2
+
+This adds device tree bindings for the Faraday FOTG2
+dual-mode host controller.
+
+Cc: ***@vger.kernel.org
+Signed-off-by: Hans Ulli Kroll <***@googlemail.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ChangeLog v1->v3:
+- Change compatible to "faraday,fotg210" as the name of the
+ hardware block.
+- Add an elaborate SoC-specific compatible string for the
+ Cortina Systems Gemini so that SoC-specific features can
+ be enabled.
+- Add cortina,gemini-mini-b to indicate a Gemini PHY with
+ a Mini-B adapter connected.
+- Indicated that the Gemini version can handle "wakeup-source".
+- Add optional IP block clock.
+---
+ .../devicetree/bindings/usb/faraday,fotg210.txt | 35 ++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/faraday,fotg210.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/faraday,fotg210.txt
+@@ -0,0 +1,35 @@
++Faraday FOTG Host controller
++
++This OTG-capable USB host controller is found in Cortina Systems
++Gemini and other SoC products.
++
++Required properties:
++- compatible: should be one of:
++ "faraday,fotg210"
++ "cortina,gemini-usb", "faraday,fotg210"
++- reg: should contain one register range i.e. start and length
++- interrupts: description of the interrupt line
++
++Optional properties:
++- clocks: should contain the IP block clock
++- clock-names: should be "PCLK" for the IP block clock
++
++Required properties for "cortina,gemini-usb" compatible:
++- syscon: a phandle to the system controller to access PHY registers
++
++Optional properties for "cortina,gemini-usb" compatible:
++- cortina,gemini-mini-b: boolean property that indicates that a Mini-B
++ OTH connector is in use
++- wakeup-source: see power/wakeup-source.txt
++
++Example for Gemini:
++
++***@68000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x68000000 0x1000>;
++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cc 12>;
++ clock-names = "PCLK";
++ syscon = <&syscon>;
++ wakeup-source;
++};
diff --git a/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch b/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch
new file mode 100644
index 000000000000..862cb649093d
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0028-usb-host-fotg2-add-device-tree-probing.patch
@@ -0,0 +1,61 @@
+From 5662c553e89ac4179ec2a7a94a342ba3e5d78cf7 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <***@googlemail.com>
+Date: Thu, 9 Feb 2017 15:20:49 +0100
+Subject: [PATCH 28/31] usb: host: fotg2: add device tree probing
+
+Add device tree probing to the fotg2 driver.
+
+Signed-off-by: Hans Ulli Kroll <***@googlemail.com>
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ChangeLog v2->v3:
+- Change compatible to "faraday,fotg210" simply.
+---
+ drivers/usb/host/fotg210-hcd.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -23,6 +23,7 @@
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+ #include <linux/module.h>
++#include <linux/of.h>
+ #include <linux/device.h>
+ #include <linux/dmapool.h>
+ #include <linux/kernel.h>
+@@ -5600,6 +5601,15 @@ static int fotg210_hcd_probe(struct plat
+ if (usb_disabled())
+ return -ENODEV;
+
++ /* Right now device-tree probed devices don't get dma_mask set.
++ * Since shared usb code relies on it, set it here for now.
++ * Once we have dma capability bindings this can go away.
++ */
++
++ retval = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
++ if (retval)
++ goto fail_create_hcd;
++
+ pdev->dev.power.power_state = PMSG_ON;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+@@ -5676,9 +5686,18 @@ static int fotg210_hcd_remove(struct pla
+ return 0;
+ }
+
++#ifdef CONFIG_OF
++static const struct of_device_id fotg210_of_match[] = {
++ { .compatible = "faraday,fotg210" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, fotg210_of_match);
++#endif
++
+ static struct platform_driver fotg210_hcd_driver = {
+ .driver = {
+ .name = "fotg210-hcd",
++ .of_match_table = of_match_ptr(fotg210_of_match),
+ },
+ .probe = fotg210_hcd_probe,
+ .remove = fotg210_hcd_remove,
diff --git a/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch b/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch
new file mode 100644
index 000000000000..4a1faf938eeb
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0029-usb-host-fotg2-add-silicon-clock-handling.patch
@@ -0,0 +1,99 @@
+From acd19633751f14607ccd76f9dfde5bde7935766c Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 21 Apr 2017 20:46:12 +0200
+Subject: [PATCH 29/31] usb: host: fotg2: add silicon clock handling
+
+When used in a system with software-controller silicon clocks,
+the FOTG210 needs to grab, prepare and enable the clock.
+This is needed on for example the Cortina Gemini, where the
+platform will by default gate off the clock unless the
+peripheral (in this case the USB driver) grabs and enables
+the clock.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/usb/host/fotg210-hcd.c | 26 ++++++++++++++++++++++----
+ drivers/usb/host/fotg210.h | 3 +++
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -45,6 +45,7 @@
+ #include <linux/uaccess.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/clk.h>
+
+ #include <asm/byteorder.h>
+ #include <asm/irq.h>
+@@ -5635,7 +5636,7 @@ static int fotg210_hcd_probe(struct plat
+ hcd->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(hcd->regs)) {
+ retval = PTR_ERR(hcd->regs);
+- goto failed;
++ goto failed_put_hcd;
+ }
+
+ hcd->rsrc_start = res->start;
+@@ -5645,22 +5646,35 @@ static int fotg210_hcd_probe(struct plat
+
+ fotg210->caps = hcd->regs;
+
++ /* It's OK not to supply this clock */
++ fotg210->pclk = clk_get(dev, "PCLK");
++ if (!IS_ERR(fotg210->pclk)) {
++ retval = clk_prepare_enable(fotg210->pclk);
++ if (retval) {
++ dev_err(dev, "failed to enable PCLK\n");
++ goto failed_dis_clk;
++ }
++ }
++
+ retval = fotg210_setup(hcd);
+ if (retval)
+- goto failed;
++ goto failed_dis_clk;
+
+ fotg210_init(fotg210);
+
+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
+ if (retval) {
+ dev_err(dev, "failed to add hcd with err %d\n", retval);
+- goto failed;
++ goto failed_dis_clk;
+ }
+ device_wakeup_enable(hcd->self.controller);
+
+ return retval;
+
+-failed:
++failed_dis_clk:
++ if (!IS_ERR(fotg210->pclk))
++ clk_disable_unprepare(fotg210->pclk);
++failed_put_hcd:
+ usb_put_hcd(hcd);
+ fail_create_hcd:
+ dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
+@@ -5676,6 +5690,10 @@ static int fotg210_hcd_remove(struct pla
+ {
+ struct device *dev = &pdev->dev;
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
++ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
++
++ if (!IS_ERR(fotg210->pclk))
++ clk_disable_unprepare(fotg210->pclk);
+
+ if (!hcd)
+ return 0;
+--- a/drivers/usb/host/fotg210.h
++++ b/drivers/usb/host/fotg210.h
+@@ -182,6 +182,9 @@ struct fotg210_hcd { /* one per contro
+ # define COUNT(x)
+ #endif
+
++ /* silicon clock */
++ struct clk *pclk;
++
+ /* debug files */
+ struct dentry *debug_dir;
+ };
diff --git a/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch
new file mode 100644
index 000000000000..2e781e403d6f
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch
@@ -0,0 +1,131 @@
+From e8ede0f62b39a3d3b06ae3dc04a74680a1f0a64b Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 21 Apr 2017 22:19:00 +0200
+Subject: [PATCH 30/31] usb: host: fotg2: add Gemini-specific handling
+
+The Cortina Systems Gemini has bolted on a PHY inside the
+silicon that can be handled by six bits in a MISC register in
+the system controller.
+
+If we are running on Gemini, look up a syscon regmap through
+a phandle and enable VBUS and optionally the Mini-B connector.
+
+If the device is flagged as "wakeup-source" using the standard
+DT bindings, we also enable this in the global controller for
+respective port.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+ drivers/usb/host/Kconfig | 1 +
+ drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 77 insertions(+)
+
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -375,6 +375,7 @@ config USB_ISP1362_HCD
+ config USB_FOTG210_HCD
+ tristate "FOTG210 HCD support"
+ depends on USB && HAS_DMA && HAS_IOMEM
++ select MFD_SYSCON
+ ---help---
+ Faraday FOTG210 is an OTG controller which can be configured as
+ an USB2.0 host. It is designed to meet USB2.0 EHCI specification
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -46,6 +46,10 @@
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ #include <linux/clk.h>
++#include <linux/bitops.h>
++/* For Cortina Gemini */
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
+
+ #include <asm/byteorder.h>
+ #include <asm/irq.h>
+@@ -5583,6 +5587,72 @@ static void fotg210_init(struct fotg210_
+ iowrite32(value, &fotg210->regs->otgcsr);
+ }
+
++/*
++ * Gemini-specific initialization function, only executed on the
++ * Gemini SoC using the global misc control register.
++ */
++#define GEMINI_GLOBAL_MISC_CTRL 0x30
++#define GEMINI_MISC_USB0_WAKEUP BIT(14)
++#define GEMINI_MISC_USB1_WAKEUP BIT(15)
++#define GEMINI_MISC_USB0_VBUS_ON BIT(22)
++#define GEMINI_MISC_USB1_VBUS_ON BIT(23)
++#define GEMINI_MISC_USB0_MINI_B BIT(29)
++#define GEMINI_MISC_USB1_MINI_B BIT(30)
++
++static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd)
++{
++ struct device_node *np = dev->of_node;
++ struct regmap *map;
++ bool mini_b;
++ bool wakeup;
++ u32 mask, val;
++ int ret;
++
++ map = syscon_regmap_lookup_by_phandle(np, "syscon");
++ if (IS_ERR(map)) {
++ dev_err(dev, "no syscon\n");
++ return PTR_ERR(map);
++ }
++ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b");
++ wakeup = of_property_read_bool(np, "wakeup-source");
++
++ /*
++ * Figure out if this is USB0 or USB1 by simply checking the
++ * physical base address.
++ */
++ mask = 0;
++ if (hcd->rsrc_start == 0x69000000) {
++ val = GEMINI_MISC_USB1_VBUS_ON;
++ if (mini_b)
++ val |= GEMINI_MISC_USB1_MINI_B;
++ else
++ mask |= GEMINI_MISC_USB1_MINI_B;
++ if (wakeup)
++ val |= GEMINI_MISC_USB1_WAKEUP;
++ else
++ mask |= GEMINI_MISC_USB1_WAKEUP;
++ } else {
++ val = GEMINI_MISC_USB0_VBUS_ON;
++ if (mini_b)
++ val |= GEMINI_MISC_USB0_MINI_B;
++ else
++ mask |= GEMINI_MISC_USB0_MINI_B;
++ if (wakeup)
++ val |= GEMINI_MISC_USB0_WAKEUP;
++ else
++ mask |= GEMINI_MISC_USB0_WAKEUP;
++ }
++
++ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
++ if (ret) {
++ dev_err(dev, "failed to initialize Gemini PHY\n");
++ return ret;
++ }
++
++ dev_info(dev, "initialized Gemini PHY\n");
++ return 0;
++}
++
+ /**
+ * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
+ *
+@@ -5662,6 +5732,12 @@ static int fotg210_hcd_probe(struct plat
+
+ fotg210_init(fotg210);
+
++ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
++ retval = fotg210_gemini_init(dev, hcd);
++ if (retval)
++ goto failed_dis_clk;
++ }
++
+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
+ if (retval) {
+ dev_err(dev, "failed to add hcd with err %d\n", retval);
diff --git a/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch b/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch
new file mode 100644
index 000000000000..cb6fdb875257
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch
@@ -0,0 +1,178 @@
+From dd62aee5d2d24199e71e745544e49a1a8b3c6f7a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <***@linaro.org>
+Date: Fri, 21 Apr 2017 20:50:22 +0200
+Subject: [PATCH 31/31] ARM: dts: Add the FOTG210 USB host to Gemini
+
+This adds the FOTG210 USB host controller to the Gemini
+device trees. In the main SoC DTSI it is flagged as disabled
+and then it is selectively enabled on the devices that utilize
+it (these per-platform enablements are done on the out-of-tree
+OpenWrt patch set). It is not enabled on the Itian SquareOne
+NAS/router since this instead has a VIA host controller
+soldered on the PCI port, and can gate off these USB host
+controllers.
+
+Signed-off-by: Linus Walleij <***@linaro.org>
+---
+USB maintainers: I will merge this through the ARM SoC tree,
+the patch is only included in the series for context.
+---
+ arch/arm/boot/dts/gemini-dlink-dir-685.dts | 8 ++++++++
+ arch/arm/boot/dts/gemini-nas4220b.dts | 8 ++++++++
+ arch/arm/boot/dts/gemini-rut1xx.dts | 20 ++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd111.dts | 20 ++++++++++++++++++++
+ arch/arm/boot/dts/gemini-wbd222.dts | 21 +++++++++++++++++++++
+ arch/arm/boot/dts/gemini.dtsi | 26 ++++++++++++++++++++++++++
+ 6 files changed, 103 insertions(+)
+
+--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+@@ -303,5 +303,13 @@
+ };
+ };
+ };
++
++ ***@68000000 {
++ status = "okay";
++ };
++
++ ***@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-nas4220b.dts
++++ b/arch/arm/boot/dts/gemini-nas4220b.dts
+@@ -146,5 +146,13 @@
+ ***@63000000 {
+ status = "okay";
+ };
++
++ ***@68000000 {
++ status = "okay";
++ };
++
++ ***@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-rut1xx.dts
++++ b/arch/arm/boot/dts/gemini-rut1xx.dts
+@@ -114,5 +114,25 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
++
++ ***@60000000 {
++ status = "okay";
++
++ ethernet-***@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-***@1 {
++ /* Not used in this platform */
++ };
++ };
++
++ ***@68000000 {
++ status = "okay";
++ };
++
++ ***@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini-wbd111.dts
+@@ -160,5 +160,25 @@
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+ };
++
++ ***@60000000 {
++ status = "okay";
++
++ ethernet-***@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-***@1 {
++ /* Not used in this platform */
++ };
++ };
++
++ ***@68000000 {
++ status = "okay";
++ };
++
++ ***@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini-wbd222.dts
+@@ -165,5 +165,26 @@
+ <0x6000 0 0 3 &pci_intc 1>,
+ <0x6000 0 0 4 &pci_intc 2>;
+ };
++
++ ***@60000000 {
++ status = "okay";
++
++ ethernet-***@0 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy0>;
++ };
++ ethernet-***@1 {
++ phy-mode = "rgmii";
++ phy-handle = <&phy1>;
++ };
++ };
++
++ ***@68000000 {
++ status = "okay";
++ };
++
++ ***@69000000 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/gemini.dtsi
++++ b/arch/arm/boot/dts/gemini.dtsi
+@@ -411,5 +411,31 @@
+ #size-cells = <0>;
+ status = "disabled";
+ };
++
++ ***@68000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x68000000 0x1000>;
++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_USB0>;
++ clocks = <&syscon GEMINI_CLK_GATE_USB0>;
++ clock-names = "PCLK";
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_default_pins>;
++ syscon = <&syscon>;
++ status = "disabled";
++ };
++
++ ***@69000000 {
++ compatible = "cortina,gemini-usb", "faraday,fotg210";
++ reg = <0x69000000 0x1000>;
++ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&syscon GEMINI_RESET_USB1>;
++ clocks = <&syscon GEMINI_CLK_GATE_USB1>;
++ clock-names = "PCLK";
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_default_pins>;
++ syscon = <&syscon>;
++ status = "disabled";
++ };
+ };
+ };
--
2.14.3
Linus Walleij
2018-04-04 20:34:06 UTC
Permalink
The v4.14 kernel is what we should be using so get rid of those
old patches. The old patches doesn't even support using device
tree.

Signed-off-by: Linus Walleij <***@linaro.org>
---
target/linux/gemini/config-4.4 | 165 ---------------
.../linux/gemini/patches-4.4/050-gpio-to-irq.patch | 21 --
target/linux/gemini/patches-4.4/060-cache-fa.patch | 41 ----
.../110-watchdog-add-gemini_wdt-driver.patch | 29 ---
.../111-arm-gemini-add-watchdog-device.patch | 33 ---
.../112-arm-gemini-register-watchdog-devices.patch | 40 ----
.../120-net-add-gemini-gmac-driver.patch | 20 --
.../121-arm-gemini-add-gmac-device.patch | 85 --------
.../122-arm-gemini-register-ethernet.patch | 227 ---------------------
.../130-usb-ehci-add-fot2g-driver.patch | 133 ------------
.../131-arm-gemini-add-usb-device.patch | 77 -------
.../patches-4.4/132-arm-gemini-register-usb.patch | 65 ------
.../140-arm-gemini-add-pci-support.patch | 66 ------
.../linux/gemini/patches-4.4/150-gemini-pata.patch | 192 -----------------
14 files changed, 1194 deletions(-)
delete mode 100644 target/linux/gemini/config-4.4
delete mode 100644 target/linux/gemini/patches-4.4/050-gpio-to-irq.patch
delete mode 100644 target/linux/gemini/patches-4.4/060-cache-fa.patch
delete mode 100644 target/linux/gemini/patches-4.4/110-watchdog-add-gemini_wdt-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/111-arm-gemini-add-watchdog-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/112-arm-gemini-register-watchdog-devices.patch
delete mode 100644 target/linux/gemini/patches-4.4/120-net-add-gemini-gmac-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/121-arm-gemini-add-gmac-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/122-arm-gemini-register-ethernet.patch
delete mode 100644 target/linux/gemini/patches-4.4/130-usb-ehci-add-fot2g-driver.patch
delete mode 100644 target/linux/gemini/patches-4.4/131-arm-gemini-add-usb-device.patch
delete mode 100644 target/linux/gemini/patches-4.4/132-arm-gemini-register-usb.patch
delete mode 100644 target/linux/gemini/patches-4.4/140-arm-gemini-add-pci-support.patch
delete mode 100644 target/linux/gemini/patches-4.4/150-gemini-pata.patch

diff --git a/target/linux/gemini/config-4.4 b/target/linux/gemini/config-4.4
deleted file mode 100644
index 9572196ae8b9..000000000000
--- a/target/linux/gemini/config-4.4
+++ /dev/null
@@ -1,165 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_GEMINI=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARPD is not set
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_FA=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_FA=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_FA526=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_TLB_FA=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_UART_PHYS=0x42000000
-CONFIG_DEBUG_UART_VIRT=0xf4200000
-CONFIG_DEBUG_UART_8250_SHIFT=2
-# CONFIG_DEBUG_UART_8250_WORD is not set
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-# CONFIG_DLCI is not set
-CONFIG_DMADEVICES=y
-CONFIG_DNOTIFY=y
-# CONFIG_DW_DMAC_CORE is not set
-# CONFIG_DW_DMAC_PCI is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_GEMINI_MEM_SWAP=y
-CONFIG_GEMINI_SL351X=y
-CONFIG_GEMINI_WATCHDOG=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-# CONFIG_HSU_DMA_PCI is not set
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_IRQ_WORK=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_MACH_NAS4220B is not set
-# CONFIG_MACH_RUT100 is not set
-CONFIG_MACH_WBD111=y
-CONFIG_MACH_WBD222=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_MACH_GPIO_H=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_VENDOR_GEMINI=y
-# CONFIG_OF is not set
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PATA_GEMINI=y
-CONFIG_PCI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_GEMINI=y
-# CONFIG_SCHED_HRTICK is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/gemini/patches-4.4/050-gpio-to-irq.patch b/target/linux/gemini/patches-4.4/050-gpio-to-irq.patch
deleted file mode 100644
index 757284986438..000000000000
--- a/target/linux/gemini/patches-4.4/050-gpio-to-irq.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/arch/arm/mach-gemini/gpio.c
-+++ b/arch/arm/mach-gemini/gpio.c
-@@ -196,12 +196,18 @@ static int gemini_gpio_direction_output(
- return 0;
- }
-
-+static int gemini_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return gpio + GPIO_IRQ_BASE;
-+}
-+
- static struct gpio_chip gemini_gpio_chip = {
- .label = "Gemini",
- .direction_input = gemini_gpio_direction_input,
- .get = gemini_gpio_get,
- .direction_output = gemini_gpio_direction_output,
- .set = gemini_gpio_set,
-+ .to_irq = gemini_gpio_to_irq,
- .base = 0,
- .ngpio = GPIO_PORT_NUM * 32,
- };
diff --git a/target/linux/gemini/patches-4.4/060-cache-fa.patch b/target/linux/gemini/patches-4.4/060-cache-fa.patch
deleted file mode 100644
index fc74c0af8882..000000000000
--- a/target/linux/gemini/patches-4.4/060-cache-fa.patch
+++ /dev/null
@@ -1,41 +0,0 @@
---- a/arch/arm/mm/cache-fa.S
-+++ b/arch/arm/mm/cache-fa.S
-@@ -24,7 +24,8 @@
- /*
- * The size of one data cache line.
- */
--#define CACHE_DLINESIZE 16
-+#define CACHE_DLINESIZE 16
-+#define CACHE_DLINESHIFT 4
-
- /*
- * The total size of the data cache.
-@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
- * - start - virtual start address
- * - end - virtual end address
- */
-+__flush_whole_dcache:
-+ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
-+ mov r0, #0
-+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
-+ mov pc, lr
-+
- fa_dma_inv_range:
-+ sub r3, r1, r0 @ calculate total size
-+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
-+ bhs __flush_whole_dcache @ flush whole D cache
-+
- tst r0, #CACHE_DLINESIZE - 1
- bic r0, r0, #CACHE_DLINESIZE - 1
- mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
-@@ -193,6 +204,10 @@ fa_dma_inv_range:
- * - end - virtual end address
- */
- fa_dma_clean_range:
-+ sub r3, r1, r0 @ calculate total size
-+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
-+ bhs __flush_whole_dcache @ flush whole D cache
-+
- bic r0, r0, #CACHE_DLINESIZE - 1
- 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
- add r0, r0, #CACHE_DLINESIZE
diff --git a/target/linux/gemini/patches-4.4/110-watchdog-add-gemini_wdt-driver.patch b/target/linux/gemini/patches-4.4/110-watchdog-add-gemini_wdt-driver.patch
deleted file mode 100644
index bb66ae4dd0bd..000000000000
--- a/target/linux/gemini/patches-4.4/110-watchdog-add-gemini_wdt-driver.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -229,6 +229,16 @@ config 977_WATCHDOG
-
- Not sure? It's safe to say N.
-
-+config GEMINI_WATCHDOG
-+ tristate "Gemini watchdog"
-+ depends on ARCH_GEMINI
-+ help
-+ Say Y here if to include support for the watchdog timer
-+ embedded in the Cortina Systems Gemini family of devices.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called gemini_wdt.
-+
- config IXP4XX_WATCHDOG
- tristate "IXP4xx Watchdog"
- depends on ARCH_IXP4XX
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
- obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
- obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
- obj-$(CONFIG_977_WATCHDOG) += wdt977.o
-+obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
- obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
- obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
- obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
diff --git a/target/linux/gemini/patches-4.4/111-arm-gemini-add-watchdog-device.patch b/target/linux/gemini/patches-4.4/111-arm-gemini-add-watchdog-device.patch
deleted file mode 100644
index ab32e9e84441..000000000000
--- a/target/linux/gemini/patches-4.4/111-arm-gemini-add-watchdog-device.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -116,3 +116,20 @@ int __init platform_register_rtc(void)
- return platform_device_register(&gemini_rtc_device);
- }
-
-+static struct resource wdt_resource = {
-+ .start = GEMINI_WAQTCHDOG_BASE,
-+ .end = GEMINI_WAQTCHDOG_BASE + 0x18,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device wdt_device = {
-+ .name = "gemini-wdt",
-+ .id = 0,
-+ .resource = &wdt_resource,
-+ .num_resources = 1,
-+};
-+
-+int __init platform_register_watchdog(void)
-+{
-+ return platform_device_register(&wdt_device);
-+}
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -27,6 +27,7 @@ extern int platform_register_uart(void);
- extern int platform_register_pflash(unsigned int size,
- struct mtd_partition *parts,
- unsigned int nr_parts);
-+extern int platform_register_watchdog(void);
-
- extern void gemini_restart(enum reboot_mode mode, const char *cmd);
-
diff --git a/target/linux/gemini/patches-4.4/112-arm-gemini-register-watchdog-devices.patch b/target/linux/gemini/patches-4.4/112-arm-gemini-register-watchdog-devices.patch
deleted file mode 100644
index d7660be4ec98..000000000000
--- a/target/linux/gemini/patches-4.4/112-arm-gemini-register-watchdog-devices.patch
+++ /dev/null
@@ -1,40 +0,0 @@
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -94,6 +94,7 @@ static void __init ib4220b_init(void)
- platform_device_register(&ib4220b_led_device);
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -121,6 +121,7 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_leds_device);
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -121,6 +121,7 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_leds_device);
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -80,6 +80,7 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_leds);
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
-+ platform_register_watchdog();
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
diff --git a/target/linux/gemini/patches-4.4/120-net-add-gemini-gmac-driver.patch b/target/linux/gemini/patches-4.4/120-net-add-gemini-gmac-driver.patch
deleted file mode 100644
index be11ae2423d5..000000000000
--- a/target/linux/gemini/patches-4.4/120-net-add-gemini-gmac-driver.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -73,6 +73,7 @@ source "drivers/net/ethernet/neterion/Kc
- source "drivers/net/ethernet/faraday/Kconfig"
- source "drivers/net/ethernet/freescale/Kconfig"
- source "drivers/net/ethernet/fujitsu/Kconfig"
-+source "drivers/net/ethernet/gemini/Kconfig"
- source "drivers/net/ethernet/hisilicon/Kconfig"
- source "drivers/net/ethernet/hp/Kconfig"
- source "drivers/net/ethernet/ibm/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_NET_VENDOR_EXAR) += neterio
- obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/
- obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/
- obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/
-+obj-$(CONFIG_NET_VENDOR_GEMINI) += gemini/
- obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/
- obj-$(CONFIG_NET_VENDOR_HP) += hp/
- obj-$(CONFIG_NET_VENDOR_IBM) += ibm/
diff --git a/target/linux/gemini/patches-4.4/121-arm-gemini-add-gmac-device.patch b/target/linux/gemini/patches-4.4/121-arm-gemini-add-gmac-device.patch
deleted file mode 100644
index 6e77224906de..000000000000
--- a/target/linux/gemini/patches-4.4/121-arm-gemini-add-gmac-device.patch
+++ /dev/null
@@ -1,85 +0,0 @@
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -15,6 +15,7 @@
- #include <linux/reboot.h>
-
- struct mtd_partition;
-+struct gemini_gmac_platform_data;
-
- extern void gemini_map_io(void);
- extern void gemini_init_irq(void);
-@@ -28,6 +29,7 @@ extern int platform_register_pflash(unsi
- struct mtd_partition *parts,
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
-+extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-
- extern void gemini_restart(enum reboot_mode mode, const char *cmd);
-
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -17,6 +17,7 @@
- #include <mach/irqs.h>
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include <mach/gmac.h>
-
- static struct plat_serial8250_port serial_platform_data[] = {
- {
-@@ -133,3 +134,56 @@ int __init platform_register_watchdog(vo
- {
- return platform_device_register(&wdt_device);
- }
-+
-+static struct resource gmac_resources[] = {
-+ {
-+ .start = GEMINI_TOE_BASE,
-+ .end = GEMINI_TOE_BASE + 0xffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_GMAC0,
-+ .end = IRQ_GMAC0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ .start = IRQ_GMAC1,
-+ .end = IRQ_GMAC1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 gmac_dmamask = 0xffffffffUL;
-+
-+static struct platform_device ethernet_device = {
-+ .name = "gmac-gemini",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &gmac_dmamask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(gmac_resources),
-+ .resource = gmac_resources,
-+};
-+
-+int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
-+{
-+ unsigned int reg;
-+
-+ reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+
-+ reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
-+
-+ if (pdata->bus_id[1])
-+ reg |= GMAC_1_ENABLE;
-+ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
-+ reg |= GMAC_GMII;
-+
-+ writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+
-+ ethernet_device.dev.platform_data = pdata;
-+
-+ return platform_device_register(&ethernet_device);
-+}
diff --git a/target/linux/gemini/patches-4.4/122-arm-gemini-register-ethernet.patch b/target/linux/gemini/patches-4.4/122-arm-gemini-register-ethernet.patch
deleted file mode 100644
index 1cd9efc20f63..000000000000
--- a/target/linux/gemini/patches-4.4/122-arm-gemini-register-ethernet.patch
+++ /dev/null
@@ -1,227 +0,0 @@
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -19,6 +19,7 @@
- #include <linux/input.h>
- #include <linux/gpio_keys.h>
- #include <linux/io.h>
-+#include <linux/platform_data/mdio-gpio.h>
-
- #include <asm/setup.h>
- #include <asm/mach-types.h>
-@@ -27,9 +28,27 @@
-
- #include <mach/hardware.h>
- #include <mach/global_reg.h>
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data ib4220b_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device ib4220b_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = { .platform_data = &ib4220b_mdio, },
-+};
-+
-+static struct gemini_gmac_platform_data ib4220b_gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_RGMII,
-+};
-+
- static struct gpio_led ib4220b_leds[] = {
- {
- .name = "nas4220b:orange:hdd",
-@@ -86,15 +105,47 @@ static struct platform_device ib4220b_ke
- },
- };
-
-+static void __init ib4220b_gmac_init(void)
-+{
-+ unsigned int val;
-+
-+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_IO_DRIVING_CTRL));
-+ val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT);
-+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_IO_DRIVING_CTRL));
-+
-+ val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) |
-+ (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xb << GMAC0_TXC_SKEW_SHIFT) |
-+ (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) |
-+ (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT);
-+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_GMAC_CTRL_SKEW_CTRL));
-+
-+ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_GMAC0_DATA_SKEW_CTRL));
-+ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_GMAC1_DATA_SKEW_CTRL));
-+
-+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_ARBITRATION1_CTRL)) & ~BURST_LENGTH_MASK;
-+ val |= (0x20 << BURST_LENGTH_SHIFT) | GMAC0_HIGH_PRIO | GMAC1_HIGH_PRIO;
-+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_ARBITRATION1_CTRL));
-+}
-+
- static void __init ib4220b_init(void)
- {
- gemini_gpio_init();
-+ ib4220b_gmac_init();
- platform_register_uart();
- platform_register_pflash(SZ_16M, NULL, 0);
- platform_device_register(&ib4220b_led_device);
- platform_device_register(&ib4220b_key_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&ib4220b_phy_device);
-+ platform_register_ethernet(&ib4220b_gmac_data);
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -17,13 +17,34 @@
- #include <linux/gpio_keys.h>
- #include <linux/mtd/mtd.h>
- #include <linux/mtd/partitions.h>
-+#include <linux/platform_data/mdio-gpio.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd111_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device wbd111_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd111_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd111_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -122,6 +143,8 @@ static void __init wbd111_init(void)
- platform_device_register(&wbd111_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd111_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -17,13 +17,36 @@
- #include <linux/gpio_keys.h>
- #include <linux/mtd/mtd.h>
- #include <linux/mtd/partitions.h>
-+#include <linux/platform_data/mdio-gpio.h>
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-
- #include "common.h"
-
-+static struct mdio_gpio_platform_data wbd222_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~((1 << 1) | (1 << 3)),
-+};
-+
-+static struct platform_device wbd222_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &wbd222_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+ .bus_id[1] = "gpio-0:03",
-+ .interface[1] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button wbd222_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -122,6 +145,8 @@ static void __init wbd222_init(void)
- platform_device_register(&wbd222_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&wbd222_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -15,13 +15,35 @@
- #include <linux/input.h>
- #include <linux/gpio_keys.h>
- #include <linux/sizes.h>
-+#include <linux/platform_data/mdio-gpio.h>
-
- #include <asm/mach-types.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/time.h>
-
-+#include <mach/gmac.h>
-+
- #include "common.h"
-
-+static struct mdio_gpio_platform_data rut1xx_mdio = {
-+ .mdc = 22,
-+ .mdio = 21,
-+ .phy_mask = ~(1 << 1),
-+};
-+
-+static struct platform_device rut1xx_phy_device = {
-+ .name = "mdio-gpio",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &rut1xx_mdio,
-+ },
-+};
-+
-+static struct gemini_gmac_platform_data gmac_data = {
-+ .bus_id[0] = "gpio-0:01",
-+ .interface[0] = PHY_INTERFACE_MODE_MII,
-+};
-+
- static struct gpio_keys_button rut1xx_keys[] = {
- {
- .code = KEY_SETUP,
-@@ -81,6 +103,8 @@ static void __init rut1xx_init(void)
- platform_device_register(&rut1xx_keys_device);
- platform_register_rtc();
- platform_register_watchdog();
-+ platform_device_register(&rut1xx_phy_device);
-+ platform_register_ethernet(&gmac_data);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
diff --git a/target/linux/gemini/patches-4.4/130-usb-ehci-add-fot2g-driver.patch b/target/linux/gemini/patches-4.4/130-usb-ehci-add-fot2g-driver.patch
deleted file mode 100644
index 2192ad69bad0..000000000000
--- a/target/linux/gemini/patches-4.4/130-usb-ehci-add-fot2g-driver.patch
+++ /dev/null
@@ -1,133 +0,0 @@
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -352,11 +352,13 @@ static void ehci_silence_controller(stru
- ehci->rh_state = EHCI_RH_HALTED;
- ehci_turn_off_all_ports(ehci);
-
-+#ifndef CONFIG_ARCH_GEMINI
- /* make BIOS/etc use companion controller during reboot */
- ehci_writel(ehci, 0, &ehci->regs->configured_flag);
-
- /* unblock posted writes */
- ehci_readl(ehci, &ehci->regs->configured_flag);
-+#endif
- spin_unlock_irq(&ehci->lock);
- }
-
-@@ -608,7 +610,9 @@ static int ehci_run (struct usb_hcd *hcd
- // Philips, Intel, and maybe others need CMD_RUN before the
- // root hub will detect new devices (why?); NEC doesn't
- ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-+#ifndef CONFIG_ARCH_GEMINI
- ehci->command |= CMD_RUN;
-+#endif
- ehci_writel(ehci, ehci->command, &ehci->regs->command);
- dbg_cmd (ehci, "init", ehci->command);
-
-@@ -628,9 +632,11 @@ static int ehci_run (struct usb_hcd *hcd
- */
- down_write(&ehci_cf_port_reset_rwsem);
- ehci->rh_state = EHCI_RH_RUNNING;
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
- ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
- msleep(5);
-+#endif
- up_write(&ehci_cf_port_reset_rwsem);
- ehci->last_periodic_enable = ktime_get_real();
-
-@@ -768,9 +774,10 @@ static irqreturn_t ehci_irq (struct usb_
- pcd_status = status;
-
- /* resume root hub? */
-+#ifndef CONFIG_ARCH_GEMINI
- if (ehci->rh_state == EHCI_RH_SUSPENDED)
- usb_hcd_resume_root_hub(hcd);
--
-+#endif
- /* get per-port change detect bits */
- if (ehci->has_ppcd)
- ppcd = status >> 16;
-@@ -1296,6 +1303,11 @@ MODULE_LICENSE ("GPL");
- #define PLATFORM_DRIVER ehci_hcd_sead3_driver
- #endif
-
-+#ifdef CONFIG_ARCH_GEMINI
-+#include "ehci-fotg2.c"
-+#define PLATFORM_DRIVER ehci_fotg2_driver
-+#endif
-+
- static int __init ehci_hcd_init(void)
- {
- int retval = 0;
---- a/drivers/usb/host/ehci-timer.c
-+++ b/drivers/usb/host/ehci-timer.c
-@@ -208,7 +208,9 @@ static void ehci_handle_controller_death
-
- /* Clean up the mess */
- ehci->rh_state = EHCI_RH_HALTED;
-+#ifndef CONFIG_ARCH_GEMINI
- ehci_writel(ehci, 0, &ehci->regs->configured_flag);
-+#endif
- ehci_writel(ehci, 0, &ehci->regs->intr_enable);
- ehci_work(ehci);
- end_unlink_async(ehci);
---- a/drivers/usb/host/ehci.h
-+++ b/drivers/usb/host/ehci.h
-@@ -657,7 +657,12 @@ static inline unsigned int
- ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
- {
- if (ehci_is_TDI(ehci)) {
-- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
-+#ifdef CONFIG_ARCH_GEMINI
-+ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
-+ switch ((portsc>>22)&3) {
-+#else
-+ switch ((portsc>>26)&3) {
-+#endif
- case 0:
- return 0;
- case 1:
---- a/drivers/usb/host/ehci-hub.c
-+++ b/drivers/usb/host/ehci-hub.c
-@@ -1076,6 +1076,11 @@ int ehci_hub_control(
- /* see what we found out */
- temp = check_reset_complete (ehci, wIndex, status_reg,
- ehci_readl(ehci, status_reg));
-+#ifdef CONFIG_ARCH_GEMINI
-+ /* restart schedule */
-+ ehci->command |= CMD_RUN;
-+ ehci_writel(ehci, ehci->command, &ehci->regs->command);
-+#endif
- }
-
- /* transfer dedicated ports to the companion hc */
---- a/include/linux/usb/ehci_def.h
-+++ b/include/linux/usb/ehci_def.h
-@@ -112,8 +112,13 @@ struct ehci_regs {
- u32 frame_list; /* points to periodic list */
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
--
-+#ifndef CONFIG_ARCH_GEMINI
- u32 reserved1[2];
-+#else
-+ u32 reserved1;
-+ /* PORTSC: offset 0x20 for Faraday OTG */
-+ u32 port_status[1];
-+#endif
-
- /* TXFILLTUNING: offset 0x24 */
- u32 txfill_tuning; /* TX FIFO Tuning register */
-@@ -125,8 +130,11 @@ struct ehci_regs {
- u32 configured_flag;
- #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
-
-+#ifndef CONFIG_ARCH_GEMINI
- /* PORTSC: offset 0x44 */
- u32 port_status[0]; /* up to N_PORTS */
-+#endif
-+
- /* EHCI 1.1 addendum */
- #define PORTSC_SUSPEND_STS_ACK 0
- #define PORTSC_SUSPEND_STS_NYET 1
diff --git a/target/linux/gemini/patches-4.4/131-arm-gemini-add-usb-device.patch b/target/linux/gemini/patches-4.4/131-arm-gemini-add-usb-device.patch
deleted file mode 100644
index a75a5c1c6ca1..000000000000
--- a/target/linux/gemini/patches-4.4/131-arm-gemini-add-usb-device.patch
+++ /dev/null
@@ -1,77 +0,0 @@
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -187,3 +187,64 @@ int platform_register_ethernet(struct ge
-
- return platform_device_register(&ethernet_device);
- }
-+
-+static struct resource usb0_resources[] = {
-+ {
-+ .start = GEMINI_USB0_BASE,
-+ .end = GEMINI_USB0_BASE + 0xfff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB0,
-+ .end = IRQ_USB0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct resource usb1_resources[] = {
-+ {
-+ .start = GEMINI_USB1_BASE,
-+ .end = GEMINI_USB1_BASE + 0xfff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_USB1,
-+ .end = IRQ_USB1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 usb0_dmamask = 0xffffffffUL;
-+static u64 usb1_dmamask = 0xffffffffUL;
-+
-+static struct platform_device usb_device[] = {
-+ {
-+ .name = "ehci-fotg2",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &usb0_dmamask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(usb0_resources),
-+ .resource = usb0_resources,
-+ },
-+ {
-+ .name = "ehci-fotg2",
-+ .id = 1,
-+ .dev = {
-+ .dma_mask = &usb1_dmamask,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(usb1_resources),
-+ .resource = usb1_resources,
-+ },
-+};
-+
-+int __init platform_register_usb(unsigned int id)
-+{
-+ if (id > 1)
-+ return -EINVAL;
-+
-+ return platform_device_register(&usb_device[id]);
-+}
-+
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -30,6 +30,7 @@ extern int platform_register_pflash(unsi
- unsigned int nr_parts);
- extern int platform_register_watchdog(void);
- extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
-+extern int platform_register_usb(unsigned int id);
-
- extern void gemini_restart(enum reboot_mode mode, const char *cmd);
-
diff --git a/target/linux/gemini/patches-4.4/132-arm-gemini-register-usb.patch b/target/linux/gemini/patches-4.4/132-arm-gemini-register-usb.patch
deleted file mode 100644
index 2a61d828eade..000000000000
--- a/target/linux/gemini/patches-4.4/132-arm-gemini-register-usb.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- a/arch/arm/mach-gemini/board-wbd111.c
-+++ b/arch/arm/mach-gemini/board-wbd111.c
-@@ -145,6 +145,7 @@ static void __init wbd111_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd111_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD111, "Wiliboard WBD-111")
---- a/arch/arm/mach-gemini/board-wbd222.c
-+++ b/arch/arm/mach-gemini/board-wbd222.c
-@@ -147,6 +147,7 @@ static void __init wbd222_init(void)
- platform_register_watchdog();
- platform_device_register(&wbd222_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(WBD222, "Wiliboard WBD-222")
---- a/arch/arm/mach-gemini/board-rut1xx.c
-+++ b/arch/arm/mach-gemini/board-rut1xx.c
-@@ -105,6 +105,7 @@ static void __init rut1xx_init(void)
- platform_register_watchdog();
- platform_device_register(&rut1xx_phy_device);
- platform_register_ethernet(&gmac_data);
-+ platform_register_usb(0);
- }
-
- MACHINE_START(RUT100, "Teltonika RUT100")
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -134,10 +134,23 @@ static void __init ib4220b_gmac_init(voi
- GLOBAL_ARBITRATION1_CTRL));
- }
-
-+static void __init usb_ib4220b_init(void)
-+{
-+ unsigned int val;
-+
-+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+ val &= ~(USB0_PLUG_MINIB | USB1_PLUG_MINIB);
-+ val |= USB0_VBUS_ON | USB1_VBUS_ON;
-+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+}
-+
- static void __init ib4220b_init(void)
- {
- gemini_gpio_init();
- ib4220b_gmac_init();
-+ usb_ib4220b_init();
- platform_register_uart();
- platform_register_pflash(SZ_16M, NULL, 0);
- platform_device_register(&ib4220b_led_device);
-@@ -146,6 +159,8 @@ static void __init ib4220b_init(void)
- platform_register_watchdog();
- platform_device_register(&ib4220b_phy_device);
- platform_register_ethernet(&ib4220b_gmac_data);
-+ platform_register_usb(0);
-+ platform_register_usb(1);
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
diff --git a/target/linux/gemini/patches-4.4/140-arm-gemini-add-pci-support.patch b/target/linux/gemini/patches-4.4/140-arm-gemini-add-pci-support.patch
deleted file mode 100644
index d17b1a1f8e41..000000000000
--- a/target/linux/gemini/patches-4.4/140-arm-gemini-add-pci-support.patch
+++ /dev/null
@@ -1,66 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -399,6 +399,7 @@ config ARCH_GEMINI
- select CLKSRC_MMIO
- select CPU_FA526
- select GENERIC_CLOCKEVENTS
-+ select MIGHT_HAVE_PCI
- help
- Support for the Cortina Systems Gemini family SoCs
-
---- a/arch/arm/mach-gemini/include/mach/hardware.h
-+++ b/arch/arm/mach-gemini/include/mach/hardware.h
-@@ -68,4 +68,9 @@
- */
- #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
-
-+/*
-+ * PCI subsystem macros
-+ */
-+#define pcibios_assign_all_busses() 1
-+
- #endif
---- a/arch/arm/mach-gemini/include/mach/irqs.h
-+++ b/arch/arm/mach-gemini/include/mach/irqs.h
-@@ -43,11 +43,14 @@
-
- #define NORMAL_IRQ_NUM 32
-
--#define GPIO_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_BASE NORMAL_IRQ_NUM
-+#define PCI_IRQ_NUM 4
-+
-+#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
- #define GPIO_IRQ_NUM (3 * 32)
-
- #define ARCH_TIMER_IRQ IRQ_TIMER2
-
--#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
-+#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
-
- #endif /* __MACH_IRQS_H__ */
---- a/arch/arm/mach-gemini/Makefile
-+++ b/arch/arm/mach-gemini/Makefile
-@@ -6,6 +6,8 @@
-
- obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
-
-+obj-$(CONFIG_PCI) += pci.o
-+
- # Board-specific support
- obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
- obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
---- a/arch/arm/mach-gemini/mm.c
-+++ b/arch/arm/mach-gemini/mm.c
-@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE),
-+ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE),
-+ .length = SZ_512K,
-+ .type = MT_DEVICE,
-+ }, {
- .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
- .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
- .length = SZ_512K,
diff --git a/target/linux/gemini/patches-4.4/150-gemini-pata.patch b/target/linux/gemini/patches-4.4/150-gemini-pata.patch
deleted file mode 100644
index 1054be08b5a4..000000000000
--- a/target/linux/gemini/patches-4.4/150-gemini-pata.patch
+++ /dev/null
@@ -1,192 +0,0 @@
---- a/arch/arm/mach-gemini/include/mach/global_reg.h
-+++ b/arch/arm/mach-gemini/include/mach/global_reg.h
-@@ -227,7 +227,13 @@
- #define USB0_PLUG_MINIB (1 << 29)
- #define GMAC_GMII (1 << 28)
- #define GMAC_1_ENABLE (1 << 27)
--/* TODO: define ATA/SATA bits */
-+/* 011 - ata0 <-> sata0, sata1; bring out ata1
-+ * 010 - ata1 <-> sata1, sata0; bring out ata0
-+ * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1
-+ * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0 */
-+#define IDE_IOMUX_MASK (7 << 24)
-+#define IDE_IOMUX_SATA1_SATA0 (2 << 24)
-+#define IDE_IOMUX_SATA0_SATA1 (3 << 24)
- #define USB1_VBUS_ON (1 << 23)
- #define USB0_VBUS_ON (1 << 22)
- #define APB_CLKOUT_ENABLE (1 << 21)
---- a/arch/arm/mach-gemini/irq.c
-+++ b/arch/arm/mach-gemini/irq.c
-@@ -89,6 +89,9 @@ void __init gemini_init_irq(void)
- irq_set_handler(i, handle_edge_irq);
- mode |= 1 << i;
- level |= 1 << i;
-+ } else if (i >= IRQ_IDE0 && i <= IRQ_IDE1) {
-+ irq_set_handler(i, handle_edge_irq);
-+ mode |= 1 << i;
- } else {
- irq_set_handler(i, handle_level_irq);
- }
---- a/arch/arm/mach-gemini/common.h
-+++ b/arch/arm/mach-gemini/common.h
-@@ -31,6 +31,7 @@ extern int platform_register_pflash(unsi
- extern int platform_register_watchdog(void);
- extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
- extern int platform_register_usb(unsigned int id);
-+extern int platform_register_pata(unsigned int id);
-
- extern void gemini_restart(enum reboot_mode mode, const char *cmd);
-
---- a/arch/arm/mach-gemini/devices.c
-+++ b/arch/arm/mach-gemini/devices.c
-@@ -248,3 +248,67 @@ int __init platform_register_usb(unsigne
- return platform_device_register(&usb_device[id]);
- }
-
-+static u64 pata_gemini_dmamask0 = 0xffffffffUL;
-+static u64 pata_gemini_dmamask1 = 0xffffffffUL;
-+
-+static struct resource pata_gemini_resources0[] =
-+{
-+ [0] = {
-+ .start = GEMINI_IDE0_BASE,
-+ .end = GEMINI_IDE0_BASE + 0x40,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_IDE0,
-+ .end = IRQ_IDE0,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct resource pata_gemini_resources1[] =
-+{
-+ [0] = {
-+ .start = GEMINI_IDE1_BASE,
-+ .end = GEMINI_IDE1_BASE + 0x40,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_IDE1,
-+ .end = IRQ_IDE1,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct platform_device pata_gemini_devices[] =
-+{
-+ {
-+ .name = "pata-gemini",
-+ .id = 0,
-+ .dev =
-+ {
-+ .dma_mask = &pata_gemini_dmamask0,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(pata_gemini_resources0),
-+ .resource = pata_gemini_resources0,
-+ },
-+ {
-+ .name = "pata-gemini",
-+ .id = 1,
-+ .dev =
-+ {
-+ .dma_mask = &pata_gemini_dmamask1,
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+ .num_resources = ARRAY_SIZE(pata_gemini_resources1),
-+ .resource = pata_gemini_resources1,
-+ },
-+};
-+
-+int __init platform_register_pata(unsigned int id)
-+{
-+ if (id > 1)
-+ return -EINVAL;
-+
-+ return platform_device_register(&pata_gemini_devices[id]);
-+}
---- a/arch/arm/mach-gemini/mm.c
-+++ b/arch/arm/mach-gemini/mm.c
-@@ -24,6 +24,11 @@ static struct map_desc gemini_io_desc[]
- .length = SZ_512K,
- .type = MT_DEVICE,
- }, {
-+ .virtual = (unsigned long)IO_ADDRESS(GEMINI_SATA_BASE),
-+ .pfn = __phys_to_pfn(GEMINI_SATA_BASE),
-+ .length = SZ_512K,
-+ .type = MT_DEVICE,
-+ }, {
- .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
- .pfn = __phys_to_pfn(GEMINI_UART_BASE),
- .length = SZ_512K,
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -567,6 +567,16 @@ config PATA_EP93XX
-
- If unsure, say N.
-
-+config PATA_GEMINI
-+ tristate "Gemini PATA support (Experimental)"
-+ depends on ARCH_GEMINI
-+ help
-+ This option enables support for the Gemini PATA-Controller.
-+ Note that the Gemini SoC has no native SATA-Controller but an
-+ onboard PATA-SATA bridge.
-+
-+ If unsure, say N.
-+
- config PATA_HPT366
- tristate "HPT 366/368 PATA support"
- depends on PCI
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -56,6 +56,7 @@ obj-$(CONFIG_PATA_CS5536) += pata_cs5536
- obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o
- obj-$(CONFIG_PATA_EFAR) += pata_efar.o
- obj-$(CONFIG_PATA_EP93XX) += pata_ep93xx.o
-+obj-$(CONFIG_PATA_GEMINI) += pata_gemini.o
- obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o
- obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o
- obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o
---- a/arch/arm/mach-gemini/board-nas4220b.c
-+++ b/arch/arm/mach-gemini/board-nas4220b.c
-@@ -146,11 +146,28 @@ static void __init usb_ib4220b_init(void
- GLOBAL_MISC_CTRL));
- }
-
-+static void __init sata_ib4220b_init(void)
-+{
-+ unsigned val;
-+
-+ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+ val &= ~(IDE_IOMUX_MASK | PFLASH_PADS_DISABLE);
-+ val |= IDE_PADS_ENABLE;
-+ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
-+ GLOBAL_MISC_CTRL));
-+
-+ /* enabling ports for presence detection, master only */
-+ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x18));
-+ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x1c));
-+}
-+
- static void __init ib4220b_init(void)
- {
- gemini_gpio_init();
- ib4220b_gmac_init();
- usb_ib4220b_init();
-+ sata_ib4220b_init();
- platform_register_uart();
- platform_register_pflash(SZ_16M, NULL, 0);
- platform_device_register(&ib4220b_led_device);
-@@ -161,6 +178,8 @@ static void __init ib4220b_init(void)
- platform_register_ethernet(&ib4220b_gmac_data);
- platform_register_usb(0);
- platform_register_usb(1);
-+ platform_register_pata(0);
-+ platform_register_pata(1);
- }
-
- MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
--
2.14.3
Roman Yeryomin
2018-04-09 10:38:47 UTC
Permalink
Post by Linus Walleij
This patch set forward-ports Gemini to v4.14 with as good
support as I can get.
I don't know if all or any patches actually make it through
https://dflund.se/~triad/krad/gemini/openwrt/
It would be nice if we could apply this and get a working
modernized base for the Gemini platforms.
The v4.14 is a bit patchy. With v4.16 we will be looking
pretty neat.
firmware-utils: Add the DNS-313 image header tool
gemini: Forward-port to v4.14
gemini: Add kernel v4.14 patches
gemini: Delete kernel 4.4 patches
Hi Linus, thanks for the patches!
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't
work. And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question:
did you have a chance to test it yourself on any of the boards? And if
yes, which one?

Regards,
Roman
Linus Walleij
2018-04-10 21:51:59 UTC
Permalink
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
Hm I tested mostly the rootfs and that the kernel would get to prompt.
But for my D-Link devices I tested mostly with kernel v4.16 because
I'm working close to mainline. Testing now it seems network is not
coming up here either :/ as it works like a charm on v4.16 it must
be some minor issue.

I would guess Hans Ulli Kroll can help with USB, I just applied the
patches and have nothing to test it with. I never used USB...

The v4.16 stack is pretty small and there the network for sure
works (not a finished patch set):
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git/log/?h=openwrt-v4.16

If it's hard to get v4.14 to backport we could maybe aim to
use v4.16 instead? Or is there some OpenWRT baselining involved?

Yours,
Linus Walleij
Roman Yeryomin
2018-04-11 21:37:23 UTC
Permalink
Post by Linus Walleij
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
Hm I tested mostly the rootfs and that the kernel would get to prompt.
But for my D-Link devices I tested mostly with kernel v4.16 because
I'm working close to mainline. Testing now it seems network is not
coming up here either :/ as it works like a charm on v4.16 it must
be some minor issue.
Looking at your tree...
I don't see any (affecting) differences in ethernet driver itself.
Probably it's something else.. MDIO?
Post by Linus Walleij
I would guess Hans Ulli Kroll can help with USB, I just applied the
patches and have nothing to test it with. I never used USB...
Hans, did you have a chance to test 4.14 (or 4.16) on any of gemini
boards?
Post by Linus Walleij
The v4.16 stack is pretty small and there the network for sure
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git/log/?h=openwrt-v4.16
If it's hard to get v4.14 to backport we could maybe aim to
use v4.16 instead? Or is there some OpenWRT baselining involved?
Yeah, generic comes first and that's not 10min work :)


Regards,
Roman
Roman Yeryomin
2018-04-16 00:00:44 UTC
Permalink
Post by Roman Yeryomin
Post by Linus Walleij
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
Hm I tested mostly the rootfs and that the kernel would get to prompt.
But for my D-Link devices I tested mostly with kernel v4.16 because
I'm working close to mainline. Testing now it seems network is not
coming up here either :/ as it works like a charm on v4.16 it must
be some minor issue.
Looking at your tree...
I don't see any (affecting) differences in ethernet driver itself.
Probably it's something else.. MDIO?
After looking into ethernet I've found several issues.
1. skew delay settings were not ported from old driver to dts for
nas4220b board
2. kernel config in you patches (accidentally?) disabled bridge support
3. driver crashes if you try to disable unused gmac in dts because of
access to uninitialized port(0|1) member of struct gemini_ethernet

So after fixing all above ethernet on nas4220b is working ok.

Can you confirm that after enabling bridge support back (just remove
CONFIG_BRIDGE from gemini kernel config and rebuild) ethernet comes up
on D-link boards? That is with default network config.


Regards,
Roman
Linus Walleij
2018-04-16 21:36:30 UTC
Permalink
Post by Roman Yeryomin
Post by Roman Yeryomin
Looking at your tree...
I don't see any (affecting) differences in ethernet driver itself.
Probably it's something else.. MDIO?
After looking into ethernet I've found several issues.
1. skew delay settings were not ported from old driver to dts for nas4220b
board
2. kernel config in you patches (accidentally?) disabled bridge support
3. driver crashes if you try to disable unused gmac in dts because of access
to uninitialized port(0|1) member of struct gemini_ethernet
Ouch. Sorry for my sucky backport. :(
Post by Roman Yeryomin
So after fixing all above ethernet on nas4220b is working ok.
You are my hero :)
Post by Roman Yeryomin
Can you confirm that after enabling bridge support back (just remove
CONFIG_BRIDGE from gemini kernel config and rebuild) ethernet comes up on
D-link boards? That is with default network config.
I think it's best if I test your entire set-up on the D-Link routers.
Do you have a git branch I can grab?

DNS-313 has working ethernet, DIR-685 is not yet working because
of missing upstream RTL8366RB support (working on it!) so it is
still a bit of WIP.

Yours,
Linus Walleij
Roman Yeryomin
2018-04-16 22:21:49 UTC
Permalink
Post by Linus Walleij
Post by Roman Yeryomin
Post by Roman Yeryomin
Looking at your tree...
I don't see any (affecting) differences in ethernet driver itself.
Probably it's something else.. MDIO?
After looking into ethernet I've found several issues.
1. skew delay settings were not ported from old driver to dts for nas4220b
board
2. kernel config in you patches (accidentally?) disabled bridge support
3. driver crashes if you try to disable unused gmac in dts because of access
to uninitialized port(0|1) member of struct gemini_ethernet
Ouch. Sorry for my sucky backport. :(
Post by Roman Yeryomin
So after fixing all above ethernet on nas4220b is working ok.
You are my hero :)
Post by Roman Yeryomin
Can you confirm that after enabling bridge support back (just remove
CONFIG_BRIDGE from gemini kernel config and rebuild) ethernet comes up on
D-link boards? That is with default network config.
I think it's best if I test your entire set-up on the D-Link routers.
Do you have a git branch I can grab?
Will try to prepare that tomorrow.
Target kernel config must be cleaned up, it's redundant in some places
and overrides some things which it should not.
I've managed to get usb working, it was kernel config error again (and
Hans' patch he sent earlier is actually working). But still usb has
problems, e.g. I couldn't get both ports working, only one of them.
SATA seems to be working out of the box, which is good!


Regards,
Roman
Hans Ulli Kroll
2018-04-14 17:36:53 UTC
Permalink
Hi Roman
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself

From 10be6c15addac0bdb9c2d196d450aee1fcb2070b Mon Sep 17 00:00:00 2001
From: Hans Ulli Kroll <***@googlemail.com>
Date: Sat, 14 Apr 2018 19:13:11 +0200
Subject: [PATCH] gemini: fix fotg2 stall after port reset

Signed-off-by: Hans Ulli Kroll <***@googlemail.com>
---
...b-host-fotg2-restart-hcd-after-port-reset.patch | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 target/linux/gemini/patches-4.14/0032-usb-host-fotg2-restart-hcd-after-port-reset.patch

diff --git a/target/linux/gemini/patches-4.14/0032-usb-host-fotg2-restart-hcd-after-port-reset.patch b/target/linux/gemini/patches-4.14/0032-usb-host-fotg2-restart-hcd-after-port-reset.patch
new file mode 100644
index 0000000000..3f1de0d107
--- /dev/null
+++ b/target/linux/gemini/patches-4.14/0032-usb-host-fotg2-restart-hcd-after-port-reset.patch
@@ -0,0 +1,31 @@
+From 731a2896e11b4e6a8d252e6c14edb1b09dbfcd46 Mon Sep 17 00:00:00 2001
+From: Hans Ulli Kroll <***@googlemail.com>
+Date: Sat, 14 Apr 2018 18:49:57 +0200
+Subject: [PATCH 1/2] usb: host: fotg2: restart hcd after port reset
+
+on Gemini SoC FOTG2 stalls after port reset
+rerstart the hcd.
+
+Signed-off-by: Hans Ulli Kroll <***@googlemail.com>
+---
+ drivers/usb/host/fotg210-hcd.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
+@@ -1653,6 +1653,10 @@ static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+ /* see what we found out */
+ temp = check_reset_complete(fotg210, wIndex, status_reg,
+ fotg210_readl(fotg210, status_reg));
++
++ /* restart schedule */
++ fotg210->command |= CMD_RUN;
++ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
+ }
+
+ if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
--
2.16.2

I have some other patch here which disable the resume after
usb_hcd_resume_root_hub()
But this make no sence to me.

Greetings
Hans Ulli Kroll
Roman Yeryomin
2018-04-15 17:22:01 UTC
Permalink
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+ /* see what we found out */
+ temp = check_reset_complete(fotg210, wIndex, status_reg,
+ fotg210_readl(fotg210, status_reg));
++
++ /* restart schedule */
++ fotg210->command |= CMD_RUN;
++ fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+ }
+
+ if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(


Regards,
Roman
Roman Yeryomin
2018-04-16 22:34:16 UTC
Permalink
Post by Roman Yeryomin
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+ /* see what we found out */
+ temp = check_reset_complete(fotg210, wIndex, status_reg,
+ fotg210_readl(fotg210, status_reg));
++
++ /* restart schedule */
++ fotg210->command |= CMD_RUN;
++ fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+ }
+
+ if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(
I've found why it didn't work:
[ 5.845199] Warning! fotg210_hcd should always be loaded before
uhci_hcd and ohci_hcd, not after

After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.

But there are other problems.
Second USB (USB1) port cannot be initialized and only USB0 is working:
[ 5.843831] fotg210_hcd: FOTG210 Host Controller (EHCI) Driver
[ 5.844298] pinctrl-gemini 40000000.syscon:pinctrl: ACTIVATE function
"usb" with group "usbgrp"
[ 5.845067] fotg210-hcd 68000000.usb: initialized Gemini PHY
[ 5.845095] fotg210-hcd 68000000.usb: Faraday USB2.0 Host Controller
[ 5.845176] fotg210-hcd 68000000.usb: new USB bus registered,
assigned bus number 1
[ 5.845696] fotg210-hcd 68000000.usb: irq 29, io mem 0x68000000
[ 5.877212] fotg210-hcd 68000000.usb: USB 2.0 started, EHCI 1.00
[ 5.880314] hub 1-0:1.0: USB hub found
[ 5.880546] hub 1-0:1.0: 1 port detected
[ 5.904768] pinctrl-gemini 40000000.syscon:pinctrl: pin T6 USB GNDA
U20 already requested by 68000000.usb; cannot claim for 69000000.usb
[ 5.904807] pinctrl-gemini 40000000.syscon:pinctrl: pin-305
(69000000.usb) status -22
[ 5.904845] pinctrl-gemini 40000000.syscon:pinctrl: could not request
pin 305 (T6 USB GNDA U20) from group usbgrp on device pinctrl-gemini
[ 5.904872] fotg210-hcd 69000000.usb: Error applying setting, reverse
things back
[ 5.904928] fotg210-hcd: probe of 69000000.usb failed with error -22

After removing pinctrl from USB1 it is initialized but then only USB1 is
working, USB0 is seen but there are no interrupts.
Didn't yet look at the code, maybe you will know where to fix right
away.

Regards,
Roman
Linus Walleij
2018-04-17 09:23:26 UTC
Permalink
[ 5.845199] Warning! fotg210_hcd should always be loaded before uhci_hcd
and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
I always wondered about that thing, it looks a bit puzzleing, something is not
right...

The SQ201 has a VIA Vectro VT6212LUSB 2.0 USB controller on PCI,
which is of course EHCI. EHCI req
Linus Walleij
2018-04-17 09:25:57 UTC
Permalink
On Tue, Apr 17, 2018 at 11:23 AM, Linus Walleij
Post by Linus Walleij
[ 5.845199] Warning! fotg210_hcd should always be loaded before uhci_hcd
and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
I always wondered about that thing, it looks a bit puzzleing, something is not
right...
The SQ201 has a VIA Vectro VT6212LUSB 2.0 USB controller on PCI,
which is of course EHCI. EHCI req
Damned google mail.

EHCI requires UHCI to be activated in Kconfig.

So to support all Geminis we are between a rock and a hard place
here... if I can get the fotg210 working on some board I can maybe
look into it.

But just supporting fotg210 is fine for now, the SQ201 is not a
regression, it's new stuff.

Yours,
Linus Walleij
John Crispin
2018-04-27 06:18:47 UTC
Permalink
Post by Roman Yeryomin
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although
I've
Post by Roman Yeryomin
managed to boot it (had to fix rootfs image) ethernet and usb
didn't work.
Post by Roman Yeryomin
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a
question: did
Post by Roman Yeryomin
you have a chance to test it yourself on any of the boards? And
if yes,
Post by Roman Yeryomin
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+             /* see what we found out */
+             temp = check_reset_complete(fotg210, wIndex, status_reg,
+                     fotg210_readl(fotg210, status_reg));
++
++            /* restart schedule */
++            fotg210->command |= CMD_RUN;
++            fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+         }
+
+         if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(
[    5.845199] Warning! fotg210_hcd should always be loaded before
uhci_hcd and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
But there are other problems.
[    5.843831] fotg210_hcd: FOTG210 Host Controller (EHCI) Driver
[    5.844298] pinctrl-gemini 40000000.syscon:pinctrl: ACTIVATE
function "usb" with group "usbgrp"
[    5.845067] fotg210-hcd 68000000.usb: initialized Gemini PHY
[    5.845095] fotg210-hcd 68000000.usb: Faraday USB2.0 Host Controller
[    5.845176] fotg210-hcd 68000000.usb: new USB bus registered,
assigned bus number 1
[    5.845696] fotg210-hcd 68000000.usb: irq 29, io mem 0x68000000
[    5.877212] fotg210-hcd 68000000.usb: USB 2.0 started, EHCI 1.00
[    5.880314] hub 1-0:1.0: USB hub found
[    5.880546] hub 1-0:1.0: 1 port detected
[    5.904768] pinctrl-gemini 40000000.syscon:pinctrl: pin T6 USB GNDA
U20 already requested by 68000000.usb; cannot claim for 69000000.usb
[    5.904807] pinctrl-gemini 40000000.syscon:pinctrl: pin-305
(69000000.usb) status -22
[    5.904845] pinctrl-gemini 40000000.syscon:pinctrl: could not
request pin 305 (T6 USB GNDA U20) from group usbgrp  on device
pinctrl-gemini
[    5.904872] fotg210-hcd 69000000.usb: Error applying setting,
reverse things back
[    5.904928] fotg210-hcd: probe of 69000000.usb failed with error -22
After removing pinctrl from USB1 it is initialized but then only USB1
is working, USB0 is seen but there are no interrupts.
Didn't yet look at the code, maybe you will know where to fix right away.
Regards,
Roman
Hi,
how shall we proceed ? merge 1, 2 and 3, let roman fix the regressions
and then merge 4 ? or drop the series for now and let you guys send a V2
with the regression fixes integrated ?
    John
Roman Yeryomin
2018-04-29 18:32:03 UTC
Permalink
Post by John Crispin
Post by Roman Yeryomin
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+             /* see what we found out */
+             temp = check_reset_complete(fotg210, wIndex, status_reg,
+                     fotg210_readl(fotg210, status_reg));
++
++            /* restart schedule */
++            fotg210->command |= CMD_RUN;
++            fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+         }
+
+         if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(
[    5.845199] Warning! fotg210_hcd should always be loaded before
uhci_hcd and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
But there are other problems.
[    5.843831] fotg210_hcd: FOTG210 Host Controller (EHCI) Driver
[    5.844298] pinctrl-gemini 40000000.syscon:pinctrl: ACTIVATE
function "usb" with group "usbgrp"
[    5.845067] fotg210-hcd 68000000.usb: initialized Gemini PHY
[    5.845095] fotg210-hcd 68000000.usb: Faraday USB2.0 Host Controller
[    5.845176] fotg210-hcd 68000000.usb: new USB bus registered,
assigned bus number 1
[    5.845696] fotg210-hcd 68000000.usb: irq 29, io mem 0x68000000
[    5.877212] fotg210-hcd 68000000.usb: USB 2.0 started, EHCI 1.00
[    5.880314] hub 1-0:1.0: USB hub found
[    5.880546] hub 1-0:1.0: 1 port detected
[    5.904768] pinctrl-gemini 40000000.syscon:pinctrl: pin T6 USB GNDA
U20 already requested by 68000000.usb; cannot claim for 69000000.usb
[    5.904807] pinctrl-gemini 40000000.syscon:pinctrl: pin-305
(69000000.usb) status -22
[    5.904845] pinctrl-gemini 40000000.syscon:pinctrl: could not
request pin 305 (T6 USB GNDA U20) from group usbgrp  on device
pinctrl-gemini
[    5.904872] fotg210-hcd 69000000.usb: Error applying setting,
reverse things back
[    5.904928] fotg210-hcd: probe of 69000000.usb failed with error -22
After removing pinctrl from USB1 it is initialized but then only USB1
is working, USB0 is seen but there are no interrupts.
Didn't yet look at the code, maybe you will know where to fix right away.
Regards,
Roman
Hi,
how shall we proceed ? merge 1, 2 and 3, let roman fix the regressions
and then merge 4 ? or drop the series for now and let you guys send a
V2 with the regression fixes integrated ?
Hi John,
I've prepared 4.14 branch here
https://github.com/yeryomin/openwrt/commits/gemini-4.14
I think it can be merged in it's current state. The only problem I'm
aware of is that usb is not fully working (afaik, Hans is working on
it).

Linus, could you test that branch on your device and see if network is
working by default?


Regards,
Roman
John Crispin
2018-04-30 06:50:42 UTC
Permalink
Post by Roman Yeryomin
Post by John Crispin
Post by Roman Yeryomin
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board.
Although I've
Post by Roman Yeryomin
managed to boot it (had to fix rootfs image) ethernet and usb
didn't work.
Post by Roman Yeryomin
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a
question: did
Post by Roman Yeryomin
you have a chance to test it yourself on any of the boards? And
if yes,
Post by Roman Yeryomin
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+             /* see what we found out */
+             temp = check_reset_complete(fotg210, wIndex, status_reg,
+                     fotg210_readl(fotg210, status_reg));
++
++            /* restart schedule */
++            fotg210->command |= CMD_RUN;
++            fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+         }
+
+         if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(
[    5.845199] Warning! fotg210_hcd should always be loaded before
uhci_hcd and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
But there are other problems.
[    5.843831] fotg210_hcd: FOTG210 Host Controller (EHCI) Driver
[    5.844298] pinctrl-gemini 40000000.syscon:pinctrl: ACTIVATE
function "usb" with group "usbgrp"
[    5.845067] fotg210-hcd 68000000.usb: initialized Gemini PHY
[    5.845095] fotg210-hcd 68000000.usb: Faraday USB2.0 Host Controller
[    5.845176] fotg210-hcd 68000000.usb: new USB bus registered,
assigned bus number 1
[    5.845696] fotg210-hcd 68000000.usb: irq 29, io mem 0x68000000
[    5.877212] fotg210-hcd 68000000.usb: USB 2.0 started, EHCI 1.00
[    5.880314] hub 1-0:1.0: USB hub found
[    5.880546] hub 1-0:1.0: 1 port detected
[    5.904768] pinctrl-gemini 40000000.syscon:pinctrl: pin T6 USB
GNDA U20 already requested by 68000000.usb; cannot claim for
69000000.usb
[    5.904807] pinctrl-gemini 40000000.syscon:pinctrl: pin-305
(69000000.usb) status -22
[    5.904845] pinctrl-gemini 40000000.syscon:pinctrl: could not
request pin 305 (T6 USB GNDA U20) from group usbgrp  on device
pinctrl-gemini
[    5.904872] fotg210-hcd 69000000.usb: Error applying setting,
reverse things back
[    5.904928] fotg210-hcd: probe of 69000000.usb failed with error -22
After removing pinctrl from USB1 it is initialized but then only
USB1 is working, USB0 is seen but there are no interrupts.
Didn't yet look at the code, maybe you will know where to fix right away.
Regards,
Roman
Hi,
how shall we proceed ? merge 1, 2 and 3, let roman fix the regressions
and then merge 4 ? or drop the series for now and let you guys send a
V2 with the regression fixes integrated ?
Hi John,
I've prepared 4.14 branch here
https://github.com/yeryomin/openwrt/commits/gemini-4.14
I think it can be merged in it's current state. The only problem I'm
aware of is that usb is not fully working (afaik, Hans is working on it).
Linus, could you test that branch on your device and see if network is
working by default?
Regards,
Roman
Great, please send patches or a PR once you feel happy with the series.

    John
Roman Yeryomin
2018-05-01 18:44:52 UTC
Permalink
Post by Roman Yeryomin
Post by John Crispin
Post by Roman Yeryomin
Post by Hans Ulli Kroll
Hi Roman
Post by Roman Yeryomin
I have tested them quickly yesterday on nas4220b board. Although I've
managed to boot it (had to fix rootfs image) ethernet and usb didn't work.
And I didn't check anything else.
I didn't yet look at the code but before I dive there I have a question: did
you have a chance to test it yourself on any of the boards? And if yes,
which one?
I think the fotg controller gets stalled after a port reset.
Please check attached (untested) patch for openwrt.
I can test this next week by myself
+diff --git a/drivers/usb/host/fotg210-hcd.c
b/drivers/usb/host/fotg210-hcd.c
+index 2acc51b0be5a..bc9efb49adc7 100644
+--- a/drivers/usb/host/fotg210-hcd.c
++++ b/drivers/usb/host/fotg210-hcd.c
*hcd, u16 typeReq, u16 wValue,
+             /* see what we found out */
+             temp = check_reset_complete(fotg210, wIndex, status_reg,
+                     fotg210_readl(fotg210, status_reg));
++
++            /* restart schedule */
++            fotg210->command |= CMD_RUN;
++            fotg210_writel(fotg210, fotg210->command,
&fotg210->regs->command);
+         }
+
+         if (!(temp & (PORT_RESUME|PORT_RESET))) {
+--
+2.16.2
+
Didn't work for me :(
[    5.845199] Warning! fotg210_hcd should always be loaded before
uhci_hcd and ohci_hcd, not after
After fixing kernel config and applying your patch it works.
So your patch works and is needed indeed.
But there are other problems.
[    5.843831] fotg210_hcd: FOTG210 Host Controller (EHCI) Driver
[    5.844298] pinctrl-gemini 40000000.syscon:pinctrl: ACTIVATE
function "usb" with group "usbgrp"
[    5.845067] fotg210-hcd 68000000.usb: initialized Gemini PHY
[    5.845095] fotg210-hcd 68000000.usb: Faraday USB2.0 Host Controller
[    5.845176] fotg210-hcd 68000000.usb: new USB bus registered,
assigned bus number 1
[    5.845696] fotg210-hcd 68000000.usb: irq 29, io mem 0x68000000
[    5.877212] fotg210-hcd 68000000.usb: USB 2.0 started, EHCI 1.00
[    5.880314] hub 1-0:1.0: USB hub found
[    5.880546] hub 1-0:1.0: 1 port detected
[    5.904768] pinctrl-gemini 40000000.syscon:pinctrl: pin T6 USB
GNDA U20 already requested by 68000000.usb; cannot claim for
69000000.usb
[    5.904807] pinctrl-gemini 40000000.syscon:pinctrl: pin-305
(69000000.usb) status -22
[    5.904845] pinctrl-gemini 40000000.syscon:pinctrl: could not
request pin 305 (T6 USB GNDA U20) from group usbgrp  on device
pinctrl-gemini
[    5.904872] fotg210-hcd 69000000.usb: Error applying setting,
reverse things back
[    5.904928] fotg210-hcd: probe of 69000000.usb failed with error -22
After removing pinctrl from USB1 it is initialized but then only USB1
is working, USB0 is seen but there are no interrupts.
Didn't yet look at the code, maybe you will know where to fix right away.
Regards,
Roman
Hi,
how shall we proceed ? merge 1, 2 and 3, let roman fix the regressions
and then merge 4 ? or drop the series for now and let you guys send a
V2 with the regression fixes integrated ?
Hi John,
I've prepared 4.14 branch here
https://github.com/yeryomin/openwrt/commits/gemini-4.14
I think it can be merged in it's current state. The only problem I'm
aware of is that usb is not fully working (afaik, Hans is working on
it).
Linus, could you test that branch on your device and see if network is
working by default?
Linus, if you have time, could you check if this helps to bring network
up on dir-685?
https://github.com/yeryomin/openwrt/commit/b0296b1f71bd3d677c931addd6de341203fbf18f

Note I have disabled video and input drivers, since dir-685 seems is the
only board which could potentially use them. And ili display wasn't
enabled anyway.
All those modules can be enabled via kernel modules. If you could test
the needed set we could add them to dir-685 packages.


Regards,
Roman
Linus Walleij
2018-05-01 22:22:16 UTC
Permalink
Linus, if you have time, could you check if this helps to bring network up
on dir-685?
https://github.com/yeryomin/openwrt/commit/b0296b1f71bd3d677c931addd6de341203fbf18f
Wow OK I will test that too.
Note I have disabled video and input drivers, since dir-685 seems is the
only board which could potentially use them. And ili display wasn't enabled
anyway.
That's fine, it's no regression anyways. v4.16+ we can add the bizarre
graphics and input capabilities.

I was planning to port "iptraf" or something else that just use ncurses
and run that on the console, eventually so there is some use for
it.

Yours,
Linus Walleij
Linus Walleij
2018-05-05 14:32:29 UTC
Permalink
Linus, if you have time, could you check if this helps to bring network up
on dir-685?
https://github.com/yeryomin/openwrt/commit/b0296b1f71bd3d677c931addd6de341203fbf18f
Sadly not. At least not outofthebox. I do not know what other
devices using the RTL8366RB is doing apart from this.

I built the platform with this small-ish patch on top because
I needed to extract the zImage:

diff --git a/target/linux/gemini/image/Makefile
b/target/linux/gemini/image/Makefile
index 25371f6f1358..3e122fc457ae 100644
--- a/target/linux/gemini/image/Makefile
+++ b/target/linux/gemini/image/Makefile
@@ -7,9 +7,12 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk

-# Build the special D-Link DNS-313 header generator tool
-# needed to generate the hard disk boot images then
-# build D-Link DNS-313 images using the special header tool.
+# Just copy the zImage for D-Link DIR-685
+define Build/dir685-images
+ cp $(IMAGE_KERNEL) $(BIN_DIR)/$(IMG_PREFIX)-dir685-zImage
+endef
+
+# Build D-Link DNS-313 images using the special header tool.
# rootfs.tgz and rd.tgz contains nothing, we only need them
# to satisfy the boot loader on the device. The zImage is
# the only real content.
@@ -79,6 +82,8 @@ define Device/dlink-dir-685
DEVICE_TITLE := D-Link DIR-685 Xtreme N Storage Router
DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) \
kmod-switch-rtl8366rb swconfig
+ IMAGES += dir685-image
+ IMAGE/dir685-image := dir685-images
endef
TARGET_DEVICES += dlink-dir-685

But I guess I should work on getting some proper flash image support
in place for this device.

I plan to repost my mainline RTL8366RB DSA patches after
some redesign,they are still not working for me, but at least
getting better in all other aspects, except actually providing
networking :(

Yours,
Linus Walleij
Roman Yeryomin
2018-05-05 15:19:42 UTC
Permalink
Post by Linus Walleij
Linus, if you have time, could you check if this helps to bring network up
on dir-685?
https://github.com/yeryomin/openwrt/commit/b0296b1f71bd3d677c931addd6de341203fbf18f
Sadly not. At least not outofthebox. I do not know what other
devices using the RTL8366RB is doing apart from this.
What did dmesg say about it?
Did you try swconfig tool? E.g. `swconfig list` and/or `swconfig dev
switch0 show`

Regards,
Roman
Linus Walleij
2018-05-01 22:18:13 UTC
Permalink
Post by Roman Yeryomin
I've prepared 4.14 branch here
https://github.com/yeryomin/openwrt/commits/gemini-4.14
I think it can be merged in it's current state. The only problem I'm aware
of is that usb is not fully working (afaik, Hans is working on it).
I also think it should be merged as this, it will be a good base for
Hans to work on the USB stuff.
Post by Roman Yeryomin
Linus, could you test that branch on your device and see if network is
working by default?
I've pulled in the branch and building it for D-Link DNS-313 right now.

Will report back.

Yours,
Linus Walleij
Linus Walleij
2018-05-02 08:01:36 UTC
Permalink
Post by Linus Walleij
Post by Roman Yeryomin
Linus, could you test that branch on your device and see if network is
working by default?
I've pulled in the branch and building it for D-Link DNS-313 right now.
Will report back.
I found some initial snags and sent you a patch for it, mostly
some chicken-and-egg problem for harddisk boot and clumsy
attempt to patch the command line from my side that I replaced
with bootargs in the device tree.

It boots, mounts root and gets to prompt now.

I will submit the bootargs patches upstream.

There is some moaning in dmesg:

[ 10.071561] Btrfs loaded, crc32c=crc32c-generic
[ 10.105705] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.161586] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.209501] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.264368] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.312050] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.368142] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.415827] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.500774] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.548542] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.604267] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 10.651342] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.699520] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.754306] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.802014] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.855212] ehci-platform: EHCI generic platform driver
[ 10.895311] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.943323] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.998070] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.045793] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.102146] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.150097] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.205504] usbcore: registered new interface driver usb-storage
[ 11.249732] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.297491] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.345619] kmodloader: 3 modules could not be probed
[ 11.376633] kmodloader: dependency not loaded mbcache
[ 11.407619] kmodloader: dependency not loaded jbd2

I guess you see this too? Related to the USB mess I guess, we can live
with it.

Network does not come up either, I suspect it is because of missing the
Realtek PHY driver, so will investigate this further.

BTW: since OpenWRT by default loads all these RAID business
I guess we should try to get the RAID XOR engine going, I think
it's a very simple piece of hardware.

Yours,
Linus Walleij
Roman Yeryomin
2018-05-02 12:02:22 UTC
Permalink
On Wed, May 2, 2018 at 12:18 AM, Linus Walleij
Post by Linus Walleij
Post by Roman Yeryomin
Linus, could you test that branch on your device and see if network is
working by default?
I've pulled in the branch and building it for D-Link DNS-313 right now.
Will report back.
I found some initial snags and sent you a patch for it, mostly
some chicken-and-egg problem for harddisk boot and clumsy
attempt to patch the command line from my side that I replaced
with bootargs in the device tree.
It boots, mounts root and gets to prompt now.
I will submit the bootargs patches upstream.
[ 10.071561] Btrfs loaded, crc32c=crc32c-generic
[ 10.105705] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.161586] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
Oh.. wait... I've missed that DNS-313 doesn't have any onboard flash and
boots from hdd!
Seems we need CONFIG_JBD2=y and CONFIG_FS_MBCACHE=y (along with ext4 and
other fs) back.
I guess you see this too? Related to the USB mess I guess, we can live
with it.
No, I don't have the same, Raidsonic (and other boards, afaik) have
onboard flash which can be used for system.
So hard drives can be used for pure storage, which is more convenient,
IMO.
Network does not come up either, I suspect it is because of missing the
Realtek PHY driver, so will investigate this further.
Could be... what does dmesg say about that? does it read any phy_id ?
Raidsonic has Marvell 88e1116 phy but works as generic phy just fine:

[ 5.731760] Generic PHY gpio-0:01: attached PHY driver [Generic PHY]
(mii_bus:phy_addr=gpio-0:01, irq=POLL)
[ 5.731781] phy_id=0x01410e11, phy_mode=rgmii


Regards,
Roman
Linus Walleij
2018-05-02 16:42:43 UTC
Permalink
Post by Linus Walleij
Network does not come up either, I suspect it is because of missing the
Realtek PHY driver, so will investigate this further.
I found the culprit, sent you a patch adding ethernet to the
DNS-313 and Wiliboard device trees. (A variant of a patch that
is already upstream in v4.16).

Now my DNS-313 works like a charm! :D

I guess we should also update the wikipage at OpenWRT with some
instructions, I don't know how to properly do that.

Yours,
Linus Walleij
Roman Yeryomin
2018-05-04 15:26:51 UTC
Permalink
Post by Linus Walleij
[ 10.071561] Btrfs loaded, crc32c=crc32c-generic
[ 10.105705] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.161586] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.209501] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.264368] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.312050] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.368142] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.415827] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.500774] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.548542] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.604267] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 10.651342] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.699520] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.754306] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.802014] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.855212] ehci-platform: EHCI generic platform driver
[ 10.895311] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 10.943323] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 10.998070] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.045793] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.102146] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.150097] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.205504] usbcore: registered new interface driver usb-storage
[ 11.249732] jbd2: exports duplicate symbol jbd2__journal_restart
(owned by kernel)
[ 11.297491] mbcache: exports duplicate symbol __mb_cache_entry_free
(owned by kernel)
[ 11.345619] kmodloader: 3 modules could not be probed
[ 11.376633] kmodloader: dependency not loaded mbcache
[ 11.407619] kmodloader: dependency not loaded jbd2
I think those should be fixed now (after compiling in jbd2 and mbcache):
https://github.com/yeryomin/openwrt/commit/14ff513daeb81a47d179c55f440ed652e407c32b

Regards,
Roman
Linus Walleij
2018-05-04 17:15:29 UTC
Permalink
Post by Roman Yeryomin
Post by Linus Walleij
[ 11.345619] kmodloader: 3 modules could not be probed
[ 11.376633] kmodloader: dependency not loaded mbcache
[ 11.407619] kmodloader: dependency not loaded jbd2
https://github.com/yeryomin/openwrt/commit/14ff513daeb81a47d179c55f440ed652e407c32b
It's working pretty well :)

My harddisk never goes to sleep but keeps spinning due to the
missing hdparm script (I guess you dropped it), but we can
always fix that later, it would ideally need a way to indicate
that this busybox command should get built and I don't know
how to do that.

The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.

Does it need a separate kmod?

Yours,
Linus Walleij
Roman Yeryomin
2018-05-04 21:37:38 UTC
Permalink
Post by Linus Walleij
Post by Roman Yeryomin
Post by Linus Walleij
[ 11.345619] kmodloader: 3 modules could not be probed
[ 11.376633] kmodloader: dependency not loaded mbcache
[ 11.407619] kmodloader: dependency not loaded jbd2
https://github.com/yeryomin/openwrt/commit/14ff513daeb81a47d179c55f440ed652e407c32b
It's working pretty well :)
Thanks for efforts and testing! :)
Post by Linus Walleij
My harddisk never goes to sleep but keeps spinning due to the
missing hdparm script (I guess you dropped it), but we can
always fix that later, it would ideally need a way to indicate
that this busybox command should get built and I don't know
how to do that.
Yeah... that should be addressed separately.
I still have few things in TODO, will add this one too.
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.


Regards,
Roman
Linus Walleij
2018-05-04 21:49:32 UTC
Permalink
Post by Roman Yeryomin
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.
Hm I ran menuconfig and it doesn't work, and removing
tmp/ didn't help either, but selecting a different target
and then selecting CS351x again worked... shaky.

OK rebuilding this overnight and retesting.

Yours,
Linus Walleij
Linus Walleij
2018-05-05 09:25:09 UTC
Permalink
Post by Linus Walleij
Post by Roman Yeryomin
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.
Hm I ran menuconfig and it doesn't work, and removing
tmp/ didn't help either, but selecting a different target
and then selecting CS351x again worked... shaky.
OK rebuilding this overnight and retesting.
It is still not working. Do you get GPIO LEDs on your
device with this?

AFAICT the problem is that there is no script in
/etc/modules-boot.d to load the GPIO LED module.

I'm digging into it to figure out more about how this
module load is supposed to work...

Yours,
Linus Walleij
Hauke Mehrtens
2018-05-05 10:09:40 UTC
Permalink
Post by Linus Walleij
Post by Linus Walleij
Post by Roman Yeryomin
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.
Hm I ran menuconfig and it doesn't work, and removing
tmp/ didn't help either, but selecting a different target
and then selecting CS351x again worked... shaky.
OK rebuilding this overnight and retesting.
It is still not working. Do you get GPIO LEDs on your
device with this?
AFAICT the problem is that there is no script in
/etc/modules-boot.d to load the GPIO LED module.
I'm digging into it to figure out more about how this
module load is supposed to work...
AutoProbe has a optional 2. parameter for boot flags, please try to replace
AUTOLOAD:=$(call AutoProbe,<module name>)
with:
AUTOLOAD:=$(call AutoProbe,<module name>, 1)

Hauke
Linus Walleij
2018-05-05 13:35:57 UTC
Permalink
Post by Linus Walleij
Post by Linus Walleij
Post by Roman Yeryomin
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.
Hm I ran menuconfig and it doesn't work, and removing
tmp/ didn't help either, but selecting a different target
and then selecting CS351x again worked... shaky.
OK rebuilding this overnight and retesting.
It is still not working. Do you get GPIO LEDs on your
device with this?
AFAICT the problem is that there is no script in
/etc/modules-boot.d to load the GPIO LED module.
I'm digging into it to figure out more about how this
module load is supposed to work...
Sorry probably bad mechanics from my side, like replacing
the rootfs but not the kernel :(

The good news is: it works like a charm.

All vital components are running, drivers probe, modules
load correctly from the hard drive.

Tested-by: Linus Walleij <***@linaro.org>

Yours,
Linus Walleij
Roman Yeryomin
2018-05-05 15:22:03 UTC
Permalink
On Sat, May 5, 2018 at 11:25 AM, Linus Walleij
On Fri, May 4, 2018 at 11:49 PM, Linus Walleij
Post by Linus Walleij
Post by Roman Yeryomin
Post by Linus Walleij
The GPIO LEDs does not come up though?
CONFIG_LEDS_GPIO is not in config, and
/sys/class/leds is empty.
Does it need a separate kmod?
kmod-leds-gpio is part of DEFAULT_PACKAGES now
I guess you should run menuconfig and/or clean tmp/ to refresh profile
package set.
Hm I ran menuconfig and it doesn't work, and removing
tmp/ didn't help either, but selecting a different target
and then selecting CS351x again worked... shaky.
OK rebuilding this overnight and retesting.
It is still not working. Do you get GPIO LEDs on your
device with this?
AFAICT the problem is that there is no script in
/etc/modules-boot.d to load the GPIO LED module.
I'm digging into it to figure out more about how this
module load is supposed to work...
Sorry probably bad mechanics from my side, like replacing
the rootfs but not the kernel :(
The good news is: it works like a charm.
All vital components are running, drivers probe, modules
load correctly from the hard drive.
Yeah.. they should be, that's one of the most common modules here :)

On Raidsonic:
***@OpenWrt:/# lsmod | grep led
leds_gpio 2772 0
ledtrig_heartbeat 1570 0

Hans Ulli Kroll
2018-05-02 16:50:56 UTC
Permalink
Hi
Post by Linus Walleij
Post by Roman Yeryomin
I've prepared 4.14 branch here
https://github.com/yeryomin/openwrt/commits/gemini-4.14
I think it can be merged in it's current state. The only problem I'm aware
of is that usb is not fully working (afaik, Hans is working on it).
I also think it should be merged as this, it will be a good base for
Hans to work on the USB stuff.
I use vanilla kernel for testing
The USB OTG protocol is complicated enough here, I must handle three
different drivers in three different places.

Hans Ulli
Joel Wirāmu Pauling
2018-05-01 22:41:00 UTC
Permalink
I have been Eyeing your Gemni patches - any chance for support for the
Goldengate SoC found in the Almond+. Currently attempting to reuse it for a
home automation project but it's ancient kernel is terrible and even doing
basic things like vlans are horribly broken with the Securfi hacked up
NutsOS that runs on top of ancient openwrt.

-Joel
Post by Linus Walleij
This patch set forward-ports Gemini to v4.14 with as good
support as I can get.
I don't know if all or any patches actually make it through
https://dflund.se/~triad/krad/gemini/openwrt/
It would be nice if we could apply this and get a working
modernized base for the Gemini platforms.
The v4.14 is a bit patchy. With v4.16 we will be looking
pretty neat.
firmware-utils: Add the DNS-313 image header tool
gemini: Forward-port to v4.14
gemini: Add kernel v4.14 patches
gemini: Delete kernel 4.4 patches
target/linux/gemini/Makefile | 15 +-
.../linux/gemini/base-files/etc/board.d/03_hdparm | 14 +
.../base-files/lib/preinit/05_set_ether_mac_gemini | 25 +-
target/linux/gemini/config-4.14 | 587 ++++
target/linux/gemini/config-4.4 | 165 -
.../files/arch/arm/mach-gemini/include/mach/gmac.h | 21 -
.../linux/gemini/files/arch/arm/mach-gemini/pci.c | 318 --
.../linux/gemini/files/drivers/ata/pata_gemini.c | 234 --
.../files/drivers/net/ethernet/gemini/Kconfig | 31 -
.../files/drivers/net/ethernet/gemini/Makefile | 5 -
.../files/drivers/net/ethernet/gemini/sl351x.c | 2340 -------------
.../files/drivers/net/ethernet/gemini/sl351x_hw.h | 1436 --------
.../gemini/files/drivers/usb/host/ehci-fotg2.c | 258 --
.../gemini/files/drivers/watchdog/gemini_wdt.c | 378 --
target/linux/gemini/image/Makefile | 166 +-
target/linux/gemini/image/dns313-header/Makefile | 34 +
.../gemini/image/dns313-header/dns313-header.c | 239 ++
target/linux/gemini/image/slask.mk | 56 +
.../0001-cache-patch-from-OpenWRT.patch} | 9 +
...0002-pinctrl-gemini-Add-missing-functions.patch | 33 +
...ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch | 51 +
...rl-Add-skew-delay-pin-config-and-bindings.patch | 73 +
...0005-pinctrl-gemini-Use-generic-DT-parser.patch | 112 +
...-gemini-Implement-clock-skew-delay-config.patch | 280 ++
.../0007-pinctrl-gemini-Fix-GMAC-groups.patch | 186 +
...nctrl-gemini-Fix-missing-pad-descriptions.patch | 27 +
...inctrl-gemini-Add-two-missing-GPIO-groups.patch | 25 +
...0-pinctrl-gemini-Fix-usage-of-3512-groups.patch | 25 +
...trl-gemini-Support-drive-strength-setting.patch | 198 ++
...d-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch | 113 +
...s-Add-basic-devicetree-for-D-Link-DNS-313.patch | 272 ++
...RM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch | 27 +
...0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch | 74 +
...-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch | 113 +
...tchdog-gemini-ftwdt010-rename-DT-bindings.patch | 88 +
...gemini-ftwdt010-rename-driver-and-symbols.patch | 527 +++
...watchdog-ftwdt010-Make-interrupt-optional.patch | 93 +
.../0020-soc-Add-SoC-driver-for-Gemini.patch | 113 +
...t-Add-DT-bindings-for-the-Gemini-ethernet.patch | 119 +
...t-Add-a-driver-for-Gemini-gigabit-etherne.patch | 3661
++++++++++++++++++++
...23-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch | 74 +
.../0024-net-gemini-Depend-on-HAS_IOMEM.patch | 30 +
...-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch | 36 +
...r-gemini-poweroff-Avoid-spurious-poweroff.patch | 80 +
...sb-host-add-DT-bindings-for-faraday-fotg2.patch | 65 +
...28-usb-host-fotg2-add-device-tree-probing.patch | 61 +
...usb-host-fotg2-add-silicon-clock-handling.patch | 99 +
...b-host-fotg2-add-Gemini-specific-handling.patch | 131 +
...RM-dts-Add-the-FOTG210-USB-host-to-Gemini.patch | 178 +
.../linux/gemini/patches-4.4/050-gpio-to-irq.patch | 21 -
.../110-watchdog-add-gemini_wdt-driver.patch | 29 -
.../111-arm-gemini-add-watchdog-device.patch | 33 -
.../112-arm-gemini-register-watchdog-devices.patch | 40 -
.../120-net-add-gemini-gmac-driver.patch | 20 -
.../121-arm-gemini-add-gmac-device.patch | 85 -
.../122-arm-gemini-register-ethernet.patch | 227 --
.../130-usb-ehci-add-fot2g-driver.patch | 133 -
.../131-arm-gemini-add-usb-device.patch | 77 -
.../patches-4.4/132-arm-gemini-register-usb.patch | 65 -
.../140-arm-gemini-add-pci-support.patch | 66 -
.../linux/gemini/patches-4.4/150-gemini-pata.patch | 192 -
target/linux/gemini/raidsonic/config-default | 5 -
target/linux/gemini/raidsonic/target.mk | 17 -
target/linux/gemini/wiligear/target.mk | 10 -
tools/firmware-utils/Makefile | 1 +
tools/firmware-utils/src/dns313-header.c | 239 ++
66 files changed, 8277 insertions(+), 6278 deletions(-)
create mode 100755 target/linux/gemini/base-files/etc/board.d/03_hdparm
create mode 100644 target/linux/gemini/config-4.14
delete mode 100644 target/linux/gemini/config-4.4
delete mode 100644 target/linux/gemini/files/
arch/arm/mach-gemini/include/mach/gmac.h
delete mode 100644 target/linux/gemini/files/arch/arm/mach-gemini/pci.c
delete mode 100644 target/linux/gemini/files/drivers/ata/pata_gemini.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/
Kconfig
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/
Makefile
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/
sl351x.c
delete mode 100644 target/linux/gemini/files/drivers/net/ethernet/gemini/
sl351x_hw.h
delete mode 100644 target/linux/gemini/files/
drivers/usb/host/ehci-fotg2.c
delete mode 100644 target/linux/gemini/files/
drivers/watchdog/gemini_wdt.c
create mode 100644 target/linux/gemini/image/dns313-header/Makefile
create mode 100644 target/linux/gemini/image/
dns313-header/dns313-header.c
create mode 100644 target/linux/gemini/image/slask.mk
rename target/linux/gemini/{patches-4.4/060-cache-fa.patch =>
patches-4.14/0001-cache-patch-from-OpenWRT.patch} (79%)
create mode 100644 target/linux/gemini/patches-4.
14/0002-pinctrl-gemini-Add-missing-functions.patch
create mode 100644 target/linux/gemini/patches-4.
14/0003-ARM-dts-Add-TVE200-to-the-Gemini-SoC-DTSI.patch
create mode 100644 target/linux/gemini/patches-4.
14/0004-pinctrl-Add-skew-delay-pin-config-and-bindings.patch
create mode 100644 target/linux/gemini/patches-4.
14/0005-pinctrl-gemini-Use-generic-DT-parser.patch
create mode 100644 target/linux/gemini/patches-4.14/0006-pinctrl-gemini-
Implement-clock-skew-delay-config.patch
create mode 100644 target/linux/gemini/patches-4.
14/0007-pinctrl-gemini-Fix-GMAC-groups.patch
create mode 100644 target/linux/gemini/patches-4.
14/0008-pinctrl-gemini-Fix-missing-pad-descriptions.patch
create mode 100644 target/linux/gemini/patches-4.
14/0009-pinctrl-gemini-Add-two-missing-GPIO-groups.patch
create mode 100644 target/linux/gemini/patches-4.
14/0010-pinctrl-gemini-Fix-usage-of-3512-groups.patch
create mode 100644 target/linux/gemini/patches-4.14/0011-pinctrl-gemini-
Support-drive-strength-setting.patch
create mode 100644 target/linux/gemini/patches-4.
14/0012-ARM-dts-Add-ethernet-PHYs-to-the-a-bunch-of-Geminis.patch
create mode 100644 target/linux/gemini/patches-4.
14/0013-ARM-dts-Add-basic-devicetree-for-D-Link-DNS-313.patch
create mode 100644 target/linux/gemini/patches-4.
14/0014-ARM-dts-Flags-D-Link-DIR-685-I2C-bus-gpios.patch
create mode 100644 target/linux/gemini/patches-4.
14/0015-ARM-dts-Add-PCI-to-WBD111-and-WBD222.patch
create mode 100644 target/linux/gemini/patches-4.
14/0016-ARM-dts-Add-TVE-TVC-and-ILI9322-panel-to-DIR-685.patch
create mode 100644 target/linux/gemini/patches-4.14/0017-watchdog-gemini-
ftwdt010-rename-DT-bindings.patch
create mode 100644 target/linux/gemini/patches-4.14/0018-watchdog-gemini-
ftwdt010-rename-driver-and-symbols.patch
create mode 100644 target/linux/gemini/patches-4.
14/0019-watchdog-ftwdt010-Make-interrupt-optional.patch
create mode 100644 target/linux/gemini/patches-4.
14/0020-soc-Add-SoC-driver-for-Gemini.patch
create mode 100644 target/linux/gemini/patches-4.
14/0021-net-ethernet-Add-DT-bindings-for-the-Gemini-ethernet.patch
create mode 100644 target/linux/gemini/patches-4.
14/0022-net-ethernet-Add-a-driver-for-Gemini-gigabit-etherne.patch
create mode 100644 target/linux/gemini/patches-4.
14/0023-ARM-dts-Add-ethernet-to-the-Gemini-SoC.patch
create mode 100644 target/linux/gemini/patches-4.
14/0024-net-gemini-Depend-on-HAS_IOMEM.patch
create mode 100644 target/linux/gemini/patches-4.
14/0025-ARM-dts-Set-D-Link-DNS-313-SATA-to-muxmode-0.patch
create mode 100644 target/linux/gemini/patches-4.
14/0026-power-gemini-poweroff-Avoid-spurious-poweroff.patch
create mode 100644 target/linux/gemini/patches-4.14/0027-usb-host-add-DT-
bindings-for-faraday-fotg2.patch
create mode 100644 target/linux/gemini/patches-4.
14/0028-usb-host-fotg2-add-device-tree-probing.patch
create mode 100644 target/linux/gemini/patches-4.
14/0029-usb-host-fotg2-add-silicon-clock-handling.patch
create mode 100644 target/linux/gemini/patches-4.
14/0030-usb-host-fotg2-add-Gemini-specific-handling.patch
create mode 100644 target/linux/gemini/patches-4.14/0031-ARM-dts-Add-the-
FOTG210-USB-host-to-Gemini.patch
delete mode 100644 target/linux/gemini/patches-4.4/050-gpio-to-irq.patch
delete mode 100644 target/linux/gemini/patches-4.
4/110-watchdog-add-gemini_wdt-driver.patch
delete mode 100644 target/linux/gemini/patches-4.
4/111-arm-gemini-add-watchdog-device.patch
delete mode 100644 target/linux/gemini/patches-4.
4/112-arm-gemini-register-watchdog-devices.patch
delete mode 100644 target/linux/gemini/patches-4.
4/120-net-add-gemini-gmac-driver.patch
delete mode 100644 target/linux/gemini/patches-4.
4/121-arm-gemini-add-gmac-device.patch
delete mode 100644 target/linux/gemini/patches-4.
4/122-arm-gemini-register-ethernet.patch
delete mode 100644 target/linux/gemini/patches-4.
4/130-usb-ehci-add-fot2g-driver.patch
delete mode 100644 target/linux/gemini/patches-4.
4/131-arm-gemini-add-usb-device.patch
delete mode 100644 target/linux/gemini/patches-4.
4/132-arm-gemini-register-usb.patch
delete mode 100644 target/linux/gemini/patches-4.
4/140-arm-gemini-add-pci-support.patch
delete mode 100644 target/linux/gemini/patches-4.4/150-gemini-pata.patch
delete mode 100644 target/linux/gemini/raidsonic/config-default
delete mode 100644 target/linux/gemini/raidsonic/target.mk
delete mode 100644 target/linux/gemini/wiligear/target.mk
create mode 100644 tools/firmware-utils/src/dns313-header.c
--
2.14.3
_______________________________________________
openwrt-devel mailing list
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Linus Walleij
2018-05-02 08:04:22 UTC
Permalink
Post by Joel Wirāmu Pauling
any chance for support for the
Goldengate SoC found in the Almond+. Currently attempting to reuse it for a
home automation project but it's ancient kernel is terrible and even doing
basic things like vlans are horribly broken with the Securfi hacked up
NutsOS that runs on top of ancient openwrt.
No idea what SoC that is, sorry, even less do I have any development
board or anything for it... if it is a Cortina or StorLink SoC there is chance
you can reuse some of the drivers for the basic IP blocks but that is
as much as I can help.

Yours,
Linus Walleij
Joel Wirāmu Pauling
2018-05-02 08:19:37 UTC
Permalink
It's Cortina but arm7 IIRC; there was a NDA available SDK for it based on
2.6.something - which I started to go through the process of getting access
too a few years ago, but the platform was bought out by Realtek who
scuttled it as it was in competition with their own designs.

The Almond+ has Zwave and Zigbee on PCI bus and Qualcomm AR9880 AC and N
radios, and a USB3 hub. Jtag fully exposed and there is even a Touchscreen
(which I think is I2C based). It would be a nice target to get working with
trunk.

I can post uboot and jtag when I am back in front of it.

-Joel
Post by Linus Walleij
Post by Joel Wirāmu Pauling
any chance for support for the
Goldengate SoC found in the Almond+. Currently attempting to reuse it
for a
Post by Joel Wirāmu Pauling
home automation project but it's ancient kernel is terrible and even
doing
Post by Joel Wirāmu Pauling
basic things like vlans are horribly broken with the Securfi hacked up
NutsOS that runs on top of ancient openwrt.
No idea what SoC that is, sorry, even less do I have any development
board or anything for it... if it is a Cortina or StorLink SoC there is chance
you can reuse some of the drivers for the basic IP blocks but that is
as much as I can help.
Yours,
Linus Walleij
Hans Ulli Kroll
2018-05-02 16:35:19 UTC
Permalink
Hi
Post by Joel Wirāmu Pauling
It's Cortina but arm7 IIRC; there was a NDA available SDK for it based on
2.6.something - which I started to go through the process of getting access
too a few years ago, but the platform was bought out by Realtek who
scuttled it as it was in competition with their own designs.
The Almond+ has Zwave and Zigbee on PCI bus and Qualcomm AR9880 AC and N
radios, and a USB3 hub. Jtag fully exposed and there is even a Touchscreen
(which I think is I2C based). It would be a nice target to get working with
trunk.
Looking at wikidevi, this should be this one
https://wikidevi.com/wiki/Securifi_Almond%2B

There is also a spec datasheet on
http://www.cortina-access.com/dhp/download/203/996/61

Hans Ulli
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